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| author | Madhav Chauhan <madhav.chauhan@intel.com> | 2018-10-15 17:28:00 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2018-10-22 15:14:03 +0300 |
| commit | 49edbd49786ee32b24f43efd383c9e97528cc4aa (patch) | |
| tree | 6e99afc5753e68882f714eae6f4a3817d1d87d95 /drivers/gpu/drm/i915/i915_pci.c | |
| parent | 9128b10249543200fbd26758beab2e7dd93addfc (diff) | |
| download | linux-stable-49edbd49786ee32b24f43efd383c9e97528cc4aa.tar.gz linux-stable-49edbd49786ee32b24f43efd383c9e97528cc4aa.tar.bz2 linux-stable-49edbd49786ee32b24f43efd383c9e97528cc4aa.zip | |
drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers
This patch defines TRANS_DDI_FUNC_CTL and TRANS_DDI_FUNC_CTL2
registers and their bitfields for DSI. These registers are used
for enabling port sync mode, input pipe select, data lane width
configuration etc.
v2: Changes:
- Remove redundant extra line
- Correct some of bitfield definition
v3 by Jani:
- Move DSI transcoder offsets to GEN11_FEATURES
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/6b2d87db82660320be10e423742cbf5a31e18037.1539613303.git.jani.nikula@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_pci.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_pci.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 0a05cc7ace14..b86b735a8634 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -595,6 +595,9 @@ static const struct intel_device_info intel_cannonlake_info = { #define GEN11_FEATURES \ GEN10_FEATURES, \ + .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ + TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET, \ + TRANSCODER_DSI0_OFFSET, TRANSCODER_DSI1_OFFSET}, \ GEN(11), \ .ddb_size = 2048, \ .has_logical_ring_elsq = 1 |