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author | Sean Paul <seanpaul@chromium.org> | 2018-01-08 14:55:41 -0500 |
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committer | Sean Paul <seanpaul@chromium.org> | 2018-01-08 14:58:29 -0500 |
commit | 07e17a75922a593393b7eb8f73622723b76d3706 (patch) | |
tree | 75de30efd8d957ceb4a0c1b5f31bf69a56915f86 /drivers/gpu/drm/i915/i915_reg.h | |
parent | d02cf0a4f4db3bdbf1f7fa6915db0a96bd98ed9e (diff) | |
download | linux-stable-07e17a75922a593393b7eb8f73622723b76d3706.tar.gz linux-stable-07e17a75922a593393b7eb8f73622723b76d3706.tar.bz2 linux-stable-07e17a75922a593393b7eb8f73622723b76d3706.zip |
drm/i915: Add function to output Aksv over GMBUS
Once the Aksv is available in the PCH, we need to get it on the wire to
the receiver via DDC. The hardware doesn't allow us to read the value
directly, so we need to tell GMBUS to source the Aksv internally and
send it to the right offset on the receiver.
The way we do this is to initiate an indexed write where the index is
the Aksv register offset. We write dummy values to GMBUS3 as if we were
sending the key, and the hardware slips in the "real" values when it
goes out.
Changes in v2:
- None
Changes in v3:
- Uses new index write feature (Ville)
Changes in v4:
- None
Changes in v5:
- checkpatch whitespace fix
Changes in v6:
- None
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20180108195545.218615-8-seanpaul@chromium.org
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5f886c7a5870..3504cf1a2e68 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3043,6 +3043,7 @@ enum i915_power_well_id { # define GPIO_DATA_PULLUP_DISABLE (1 << 13) #define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */ +#define GMBUS_AKSV_SELECT (1<<11) #define GMBUS_RATE_100KHZ (0<<8) #define GMBUS_RATE_50KHZ (1<<8) #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ |