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| author | Matt Roper <matthew.d.roper@intel.com> | 2020-08-03 21:40:24 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2020-08-17 16:16:45 -0400 |
| commit | 3f8210fd22d0c02faa18b36974debf1ad25b7f92 (patch) | |
| tree | b33d3afa955a4137c5de811e1849060bed89d3c8 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 66b51b801d05ee54a0f23628cb8220189adb715e (diff) | |
| download | linux-stable-3f8210fd22d0c02faa18b36974debf1ad25b7f92.tar.gz linux-stable-3f8210fd22d0c02faa18b36974debf1ad25b7f92.tar.bz2 linux-stable-3f8210fd22d0c02faa18b36974debf1ad25b7f92.zip | |
Revert "drm/i915/rkl: Add Wa_14011224835 for PHY B initialization"
The hardware team has dropped this workaround from the bspec; it is no
longer needed.
This reverts commit 111822b21be995a3a4a731066db3d820523c57f7.
Bspec: 49291
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200804044024.1931170-1-matthew.d.roper@intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 13 |
1 files changed, 1 insertions, 12 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5eae593ee784..2b403df03404 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1911,16 +1911,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define CNL_PORT_COMP_DW0 _MMIO(0x162100) #define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy)) -#define COMP_INIT REG_BIT(31) -#define GRCCODE_LDO REG_GENMASK(7, 0) +#define COMP_INIT (1 << 31) #define CNL_PORT_COMP_DW1 _MMIO(0x162104) #define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy)) -#define ICL_PORT_COMP_DW2(phy) _MMIO(_ICL_PORT_COMP_DW(2, phy)) -#define IREF_RCAL_ORD_EN REG_BIT(7) -#define IREF_RCAL_ORD REG_GENMASK(6, 0) - #define CNL_PORT_COMP_DW3 _MMIO(0x16210c) #define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy)) #define PROCESS_INFO_DOT_0 (0 << 26) @@ -1933,12 +1928,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define VOLTAGE_INFO_1_05V (2 << 24) #define VOLTAGE_INFO_MASK (3 << 24) #define VOLTAGE_INFO_SHIFT 24 -#define FIRST_COMP_DONE REG_BIT(22) - -#define ICL_PORT_COMP_DW6(phy) _MMIO(_ICL_PORT_COMP_DW(6, phy)) -#define GRCCODE REG_GENMASK(30, 24) -#define RCOMPCODEOVEN_LDO_SYNC REG_BIT(23) -#define RCOMPCODE_LD_CAP_OV REG_GENMASK(22, 16) #define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy)) #define IREFGEN (1 << 24) |