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| author | Mika Kuoppala <mika.kuoppala@linux.intel.com> | 2019-04-12 19:53:53 +0300 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2019-04-12 19:23:45 +0100 |
| commit | 5ce5f61b70f97bd664f7a20aeffd9574d17ab350 (patch) | |
| tree | cfb4d788f723131176629d2bbae19f6188c96026 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 019d26004ebad73a5aedaedab958ea8a381c2ffc (diff) | |
| download | linux-stable-5ce5f61b70f97bd664f7a20aeffd9574d17ab350.tar.gz linux-stable-5ce5f61b70f97bd664f7a20aeffd9574d17ab350.tar.bz2 linux-stable-5ce5f61b70f97bd664f7a20aeffd9574d17ab350.zip | |
drm/i915: Handle catastrophic error on engine reset
If cat error is set, we need to clear it by acking it. Further,
if it is set, we must not do a normal request for reset.
v2: avoid goto (Chris)
v3: comment, error format, direct assign (Chris)
Bspec: 12567
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190412165353.16432-1-mika.kuoppala@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8ad2f0a03f28..c1c0f7ab03e9 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2446,8 +2446,10 @@ enum i915_power_well_id { #define RING_HWS_PGA(base) _MMIO((base) + 0x80) #define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080) #define RING_RESET_CTL(base) _MMIO((base) + 0xd0) -#define RESET_CTL_REQUEST_RESET (1 << 0) -#define RESET_CTL_READY_TO_RESET (1 << 1) +#define RESET_CTL_CAT_ERROR REG_BIT(2) +#define RESET_CTL_READY_TO_RESET REG_BIT(1) +#define RESET_CTL_REQUEST_RESET REG_BIT(0) + #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c) #define HSW_GTT_CACHE_EN _MMIO(0x4024) |