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| author | Imre Deak <imre.deak@intel.com> | 2019-04-25 21:52:52 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2019-05-02 17:15:09 +0300 |
| commit | bd60a562906b2dfa6db4e9165c1498ea25db0587 (patch) | |
| tree | f179c259905bccc94b368ef3d82f11446be7e5ce /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 3904fb78a80da64d7fd1a4f270725a6d4272c86f (diff) | |
| download | linux-stable-bd60a562906b2dfa6db4e9165c1498ea25db0587.tar.gz linux-stable-bd60a562906b2dfa6db4e9165c1498ea25db0587.tar.bz2 linux-stable-bd60a562906b2dfa6db4e9165c1498ea25db0587.zip | |
drm/i915/icl: Factor out combo PHY lane power setup helper
Factor out the combo PHY lane power configuration code to a separate
helper; it will be also needed by the next patch adding the same
configuration for DDI ports.
Add support for DDI ports and lane reversal as preparation for the next
patch.
The PWR_DOWN_LN_1 value is unspecified in the BSpec register description
so remove it.
v2:
- Fix up the wrong assumption that the encodings are the same for DDI
and DSI ports. (Jani)
v3:
- Use intel_ instead of icl_ prefix. (Jani)
- Add required headers to intel_combo_phy.h after the upstream header
refactoring.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com> (v2)
Link: https://patchwork.freedesktop.org/patch/msgid/20190425185253.3197-1-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f386c6c8a3b7..e97c47fca645 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1813,7 +1813,6 @@ enum i915_power_well_id { #define PWR_DOWN_LN_3 (0x8 << 4) #define PWR_DOWN_LN_2_1_0 (0x7 << 4) #define PWR_DOWN_LN_1_0 (0x3 << 4) -#define PWR_DOWN_LN_1 (0x2 << 4) #define PWR_DOWN_LN_3_1 (0xa << 4) #define PWR_DOWN_LN_3_1_0 (0xb << 4) #define PWR_DOWN_LN_MASK (0xf << 4) |