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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-02-07 22:21:42 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-02-08 14:29:39 +0200 |
| commit | 8271b2ef71aaabac452dc03a6cbe8960cbea4247 (patch) | |
| tree | 2cf522d43f154bc33dfcf0ffa2073f8407e4ede1 /drivers/gpu/drm/i915/intel_color.c | |
| parent | 5f29ab23046a4bb08a850e41bdb579b2cb59421d (diff) | |
| download | linux-stable-8271b2ef71aaabac452dc03a6cbe8960cbea4247.tar.gz linux-stable-8271b2ef71aaabac452dc03a6cbe8960cbea4247.tar.bz2 linux-stable-8271b2ef71aaabac452dc03a6cbe8960cbea4247.zip | |
drm/i915: Track pipe csc enable in crtc state
Just like we did for pipe gamma, let's also track the pipe csc
state. The hardware only exists on ILK+, and currently we always
enable it on hsw+ and never on any other platforms. Just like
with pipe gamma, the primary plane control register is used
for the readout on pre-SKL, and the pipe bottom color register
on SKL+.
v2: Rebase
v3: Allow fastboot with csc_enable changes (Maarten)
Deal with HAS_GMCH
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190207202146.26423-4-ville.syrjala@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_color.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_color.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 746138d7bcbc..e3bf3bd355ab 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -401,7 +401,8 @@ static void skl_color_commit(const struct intel_crtc_state *crtc_state) */ if (crtc_state->gamma_enable) val |= SKL_BOTTOM_COLOR_GAMMA_ENABLE; - val |= SKL_BOTTOM_COLOR_CSC_ENABLE; + if (crtc_state->csc_enable) + val |= SKL_BOTTOM_COLOR_CSC_ENABLE; I915_WRITE(SKL_BOTTOM_COLOR(pipe), val); I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode); @@ -668,6 +669,10 @@ int intel_color_check(struct intel_crtc_state *crtc_state) crtc_state->gamma_enable = true; + if (INTEL_GEN(dev_priv) >= 9 || + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) + crtc_state->csc_enable = true; + /* Always allow legacy gamma LUT with no further checking. */ if (crtc_state_is_legacy_gamma(crtc_state)) { crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT; |