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authorJani Nikula <jani.nikula@intel.com>2019-09-11 23:29:08 +0300
committerJani Nikula <jani.nikula@intel.com>2019-09-12 18:21:38 +0300
commit8d8b00318593e2852aef19b92f99851d50a203fc (patch)
treec62d1f45aa1b71aaab3a7ba3f7fbbb17770fbdfb /drivers/gpu/drm/i915/intel_device_info.c
parent54fc577d90d01a28dbfccd277aa3de4d4abaf1ff (diff)
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drm/i915: convert device info num_pipes to pipe_mask
Replace device info number of pipes with a bit mask of available pipes. This will prove handy in the future. There's still a bunch of future work to do to actually allow a non-consecutive mask of pipes, but it's a start. No functional changes. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190911202908.19631-1-jani.nikula@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_device_info.c')
-rw-r--r--drivers/gpu/drm/i915/intel_device_info.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index d9b5baaef5d0..50b05a5de53b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -896,7 +896,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
if (i915_modparams.disable_display) {
DRM_INFO("Display disabled (module parameter)\n");
- info->num_pipes = 0;
+ info->pipe_mask = 0;
} else if (HAS_DISPLAY(dev_priv) &&
(IS_GEN_RANGE(dev_priv, 7, 8)) &&
HAS_PCH_SPLIT(dev_priv)) {
@@ -917,14 +917,14 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
(HAS_PCH_CPT(dev_priv) &&
!(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
DRM_INFO("Display fused off, disabling\n");
- info->num_pipes = 0;
+ info->pipe_mask = 0;
} else if (fuse_strap & IVB_PIPE_C_DISABLE) {
DRM_INFO("PipeC fused off\n");
- info->num_pipes -= 1;
+ info->pipe_mask &= ~BIT(PIPE_C);
}
} else if (HAS_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 9) {
u32 dfsm = I915_READ(SKL_DFSM);
- u8 enabled_mask = BIT(info->num_pipes) - 1;
+ u8 enabled_mask = info->pipe_mask;
if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
enabled_mask &= ~BIT(PIPE_A);
@@ -945,7 +945,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
DRM_ERROR("invalid pipe fuse configuration: enabled_mask=0x%x\n",
enabled_mask);
else
- info->num_pipes = hweight8(enabled_mask);
+ info->pipe_mask = enabled_mask;
}
/* Initialize slice/subslice/EU info */