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| author | Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> | 2018-10-16 15:46:47 -0700 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2018-10-17 17:46:38 +0100 |
| commit | 20fd600099754bb1d29405247c6c2b74ebc3b9f2 (patch) | |
| tree | 64828ad554640121f6b6f00eec415477c44e2fa1 /drivers/gpu/drm/i915/intel_guc_fwif.h | |
| parent | 138bdac891831d3e86ee75a5217c9b0f001ab12b (diff) | |
| download | linux-stable-20fd600099754bb1d29405247c6c2b74ebc3b9f2.tar.gz linux-stable-20fd600099754bb1d29405247c6c2b74ebc3b9f2.tar.bz2 linux-stable-20fd600099754bb1d29405247c6c2b74ebc3b9f2.zip | |
drm/i915/guc: fix GuC suspend/resume
The ENTER/EXIT_S_STATE actions queue the save/restore operation in GuC
FW and then return, so waiting on the H2G is not enough to guarantee
GuC is done.
When all the processing is done, GuC writes 0 to scratch register 14,
so we can poll on that. Note that GuC does not ensure that the value
in the register is different from 0 while the action is in progress
so we need to take care of that ourselves as well.
v2: improve comment, return early on GuC error and improve error
message (Michal)
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20181016224648.2326-1-daniele.ceraolospurio@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_guc_fwif.h')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_guc_fwif.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index 8382d591c784..d1bbaba6e012 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -687,6 +687,13 @@ enum intel_guc_report_status { INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4, }; +enum intel_guc_sleep_state_status { + INTEL_GUC_SLEEP_STATE_SUCCESS = 0x0, + INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x1, + INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x2 +#define INTEL_GUC_SLEEP_STATE_INVALID_MASK 0x80000000 +}; + #define GUC_LOG_CONTROL_LOGGING_ENABLED (1 << 0) #define GUC_LOG_CONTROL_VERBOSITY_SHIFT 4 #define GUC_LOG_CONTROL_VERBOSITY_MASK (0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT) |