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| author | Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> | 2020-04-30 22:56:34 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2020-05-04 18:44:52 +0300 |
| commit | ecab0f3d055d333640bbe2aa5a5141574a65c534 (patch) | |
| tree | 5654e7b5993dd39383e84e9527e348fa3019e5dd /drivers/gpu/drm/i915/intel_pm.c | |
| parent | 9728889f42b9ba078f86cd11535a89df29e93b33 (diff) | |
| download | linux-stable-ecab0f3d055d333640bbe2aa5a5141574a65c534.tar.gz linux-stable-ecab0f3d055d333640bbe2aa5a5141574a65c534.tar.bz2 linux-stable-ecab0f3d055d333640bbe2aa5a5141574a65c534.zip | |
drm/i915: Track active_pipes in bw_state
We need to calculate SAGV mask also in a non-modeset
commit, however currently active_pipes are only calculated
for modesets in global atomic state, thus now we will be
tracking those also in bw_state in order to be able to
properly access global data.
v2: - Removed pre/post plane SAGV updates from modeset(Ville)
- Now tracking active pipes in intel_can_enable_sagv(Ville)
v3: - lock global state if active_pipes change as well(Ville)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200430195634.7666-1-stanislav.lisovskiy@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 27 |
1 files changed, 14 insertions, 13 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 29c37e4a666c..c26f87427e18 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3806,7 +3806,6 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state) static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state) { - struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_plane *plane; @@ -3819,13 +3818,6 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state if (!crtc_state->hw.active) return true; - /* - * SKL+ workaround: bspec recommends we disable SAGV when we have - * more then one pipe enabled - */ - if (hweight8(state->active_pipes) > 1) - return false; - if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) return false; @@ -3863,6 +3855,9 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state bool intel_can_enable_sagv(const struct intel_bw_state *bw_state) { + if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes)) + return false; + return bw_state->pipe_sagv_reject == 0; } @@ -3892,6 +3887,14 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state) if (!new_bw_state) return 0; + new_bw_state->active_pipes = + intel_calc_active_pipes(state, old_bw_state->active_pipes); + if (new_bw_state->active_pipes != old_bw_state->active_pipes) { + ret = intel_atomic_lock_global_state(&new_bw_state->base); + if (ret) + return ret; + } + if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) { ret = intel_atomic_serialize_global_state(&new_bw_state->base); if (ret) @@ -5866,11 +5869,9 @@ skl_compute_wm(struct intel_atomic_state *state) if (ret) return ret; - if (state->modeset) { - ret = intel_compute_sagv_mask(state); - if (ret) - return ret; - } + ret = intel_compute_sagv_mask(state); + if (ret) + return ret; /* * skl_compute_ddb() will have adjusted the final watermarks |