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| author | Mika Kuoppala <mika.kuoppala@linux.intel.com> | 2018-11-09 16:09:23 +0200 |
|---|---|---|
| committer | Mika Kuoppala <mika.kuoppala@linux.intel.com> | 2018-11-14 11:36:58 +0200 |
| commit | 8577c319b6511fbc391f3775225fecd8b979bc26 (patch) | |
| tree | 4fd44e56ece792fe3bacefff07cb1a464e780ef3 /drivers/gpu/drm/i915/intel_runtime_pm.c | |
| parent | 704e504bd6167084dd0841c02d1d2bb58889e967 (diff) | |
| download | linux-stable-8577c319b6511fbc391f3775225fecd8b979bc26.tar.gz linux-stable-8577c319b6511fbc391f3775225fecd8b979bc26.tar.bz2 linux-stable-8577c319b6511fbc391f3775225fecd8b979bc26.zip | |
drm/i915/icl: Drop spurious register read from icl_dbuf_slices_update
Register DBUF_CTL_S2 is read and it's value is not used. As
there is no explanation why we should prime the hardware with
read, remove it as spurious.
Fixes: aa9664ffe863 ("drm/i915/icl: Enable 2nd DBuf slice only when needed")
Cc: Mahesh Kumar <mahesh1.kumar@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181109140924.2663-1-mika.kuoppala@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_runtime_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_runtime_pm.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index f945db6ea420..770de2632530 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -3236,8 +3236,7 @@ static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv) void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, u8 req_slices) { - u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices; - u32 val; + const u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices; bool ret; if (req_slices > intel_dbuf_max_slices(dev_priv)) { @@ -3248,7 +3247,6 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, if (req_slices == hw_enabled_slices || req_slices == 0) return; - val = I915_READ(DBUF_CTL_S2); if (req_slices > hw_enabled_slices) ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, true); else |