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| author | Jani Nikula <jani.nikula@intel.com> | 2019-05-02 17:52:34 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2019-05-03 09:27:13 +0300 |
| commit | c9fd91668dbdace78bcb5ce40a11316448db6cf1 (patch) | |
| tree | 8e96755f139bbce103c79bd96e8c88ff85f51957 /drivers/gpu/drm/i915/intel_runtime_pm.c | |
| parent | 263a8cf1ff5ea63dc9f456829c310df35f0249aa (diff) | |
| download | linux-stable-c9fd91668dbdace78bcb5ce40a11316448db6cf1.tar.gz linux-stable-c9fd91668dbdace78bcb5ce40a11316448db6cf1.tar.bz2 linux-stable-c9fd91668dbdace78bcb5ce40a11316448db6cf1.zip | |
drm/i915: add single combo phy init/unit functions
Work on the principle that files should prefer not to expose platform
specific functions.
v2, v3: Rebase
Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190502145234.7002-1-jani.nikula@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_runtime_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_runtime_pm.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 30e7cb9d5801..be71197abc00 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -1140,7 +1140,7 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, * PHY's HW context for port B is lost after DC transitions, * so we need to restore it manually. */ - icl_combo_phys_init(dev_priv); + intel_combo_phy_init(dev_priv); } static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, @@ -3779,7 +3779,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); /* 2-3. */ - cnl_combo_phys_init(dev_priv); + intel_combo_phy_init(dev_priv); /* * 4. Enable Power Well 1 (PG1). @@ -3828,7 +3828,7 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv) usleep_range(10, 30); /* 10 us delay per Bspec */ /* 5. */ - cnl_combo_phys_uninit(dev_priv); + intel_combo_phy_uninit(dev_priv); } void icl_display_core_init(struct drm_i915_private *dev_priv, @@ -3843,7 +3843,7 @@ void icl_display_core_init(struct drm_i915_private *dev_priv, intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); /* 2. Initialize all combo phys */ - icl_combo_phys_init(dev_priv); + intel_combo_phy_init(dev_priv); /* * 3. Enable Power Well 1 (PG1). @@ -3893,7 +3893,7 @@ void icl_display_core_uninit(struct drm_i915_private *dev_priv) mutex_unlock(&power_domains->lock); /* 5. */ - icl_combo_phys_uninit(dev_priv); + intel_combo_phy_uninit(dev_priv); } static void chv_phy_control_init(struct drm_i915_private *dev_priv) |