summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/intel_sideband.h
diff options
context:
space:
mode:
authorVille Syrjälä <ville.syrjala@linux.intel.com>2019-05-21 19:40:24 +0300
committerVille Syrjälä <ville.syrjala@linux.intel.com>2019-05-27 20:51:48 +0300
commitd284d5145eb8760b592e64249c1cd85c440fe90f (patch)
treeeae3c8bda3e46444a61f69d1e77d8e633b448f01 /drivers/gpu/drm/i915/intel_sideband.h
parent4361ccac2810553d6cfaa6860bd4bd65f4742ed2 (diff)
downloadlinux-stable-d284d5145eb8760b592e64249c1cd85c440fe90f.tar.gz
linux-stable-d284d5145eb8760b592e64249c1cd85c440fe90f.tar.bz2
linux-stable-d284d5145eb8760b592e64249c1cd85c440fe90f.zip
drm/i915: Make sandybridge_pcode_read() deal with the second data register
The pcode mailbox has two data registers. So far we've only ever used the one, but that's about to change. Expose the second data register to the callers of sandybridge_pcode_read(). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com> Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190521164025.30225-1-ville.syrjala@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_sideband.h')
-rw-r--r--drivers/gpu/drm/i915/intel_sideband.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_sideband.h b/drivers/gpu/drm/i915/intel_sideband.h
index a0907e2c4992..7fb95745a444 100644
--- a/drivers/gpu/drm/i915/intel_sideband.h
+++ b/drivers/gpu/drm/i915/intel_sideband.h
@@ -127,7 +127,8 @@ u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg,
void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value,
enum intel_sbi_destination destination);
-int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val);
+int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox,
+ u32 *val, u32 *val1);
int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox,
u32 val, int fast_timeout_us,
int slow_timeout_ms);