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author | Michal Wajdeczko <michal.wajdeczko@intel.com> | 2017-05-10 12:59:27 +0000 |
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committer | Joonas Lahtinen <joonas.lahtinen@linux.intel.com> | 2017-05-11 12:49:26 +0300 |
commit | a0c1fe219080d6b23270d5c7f7d773e7d753177a (patch) | |
tree | 0a117031cfdf6717c1a1f249c70b352b66d12225 /drivers/gpu/drm/i915/intel_uc.h | |
parent | a03aac442d6f4ca4525e526047d831efb77b436a (diff) | |
download | linux-stable-a0c1fe219080d6b23270d5c7f7d773e7d753177a.tar.gz linux-stable-a0c1fe219080d6b23270d5c7f7d773e7d753177a.tar.bz2 linux-stable-a0c1fe219080d6b23270d5c7f7d773e7d753177a.zip |
drm/i915/guc: Make scratch register base and count flexible
We are using some scratch registers in MMIO based send function.
Make their base and count flexible in preparation of upcoming
GuC firmware/hardware changes. While around, change cmd len
parameter verification from WARN_ON to GEM_BUG_ON as we don't
need this all the time.
v2: call out WARN/GEM_BUG change in the commit msg (Daniele)
v3: don't overqualify the ints (Chris)
v4: rebase and use proper enum
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Suggested-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_uc.h')
-rw-r--r-- | drivers/gpu/drm/i915/intel_uc.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h index 2af5633b8a09..7618b7100175 100644 --- a/drivers/gpu/drm/i915/intel_uc.h +++ b/drivers/gpu/drm/i915/intel_uc.h @@ -205,6 +205,13 @@ struct intel_guc { uint64_t submissions[I915_NUM_ENGINES]; uint32_t last_seqno[I915_NUM_ENGINES]; + /* GuC's FW specific registers used in MMIO send */ + struct { + u32 base; + unsigned int count; + enum forcewake_domains fw_domains; + } send_regs; + /* To serialize the intel_guc_send actions */ struct mutex send_mutex; |