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| author | Wangyan Wang <wangyan.wang@mediatek.com> | 2019-04-09 14:53:07 +0800 |
|---|---|---|
| committer | CK Hu <ck.hu@mediatek.com> | 2019-04-09 17:47:01 +0800 |
| commit | 9ee76098a1b8ae21cccac641b735ee4d3a77bccf (patch) | |
| tree | 083e3312f604a323692227932ab48bb6f985404d /drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | |
| parent | 8eeb3946feeb00486ac0909e2309da87db8988a5 (diff) | |
| download | linux-stable-9ee76098a1b8ae21cccac641b735ee4d3a77bccf.tar.gz linux-stable-9ee76098a1b8ae21cccac641b735ee4d3a77bccf.tar.bz2 linux-stable-9ee76098a1b8ae21cccac641b735ee4d3a77bccf.zip | |
drm/mediatek: no change parent rate in round_rate() for MT2701 hdmi phy
This is the third step to make MT2701 HDMI stable.
We should not change the rate of parent for hdmi phy when
doing round_rate for this clock. The parent clock of hdmi
phy must be the same as it. We change it when doing set_rate
only.
Signed-off-by: Wangyan Wang <wangyan.wang@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Diffstat (limited to 'drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c')
| -rw-r--r-- | drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c index 37f9503d7643..47f8a2951682 100644 --- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c +++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c @@ -199,6 +199,20 @@ static void mtk_hdmi_pll_unprepare(struct clk_hw *hw) usleep_range(100, 150); } +static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); + + hdmi_phy->pll_rate = rate; + if (rate <= 74250000) + *parent_rate = rate; + else + *parent_rate = rate / 2; + + return rate; +} + static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { |