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| author | Arnaud Vrac <avrac@freebox.fr> | 2023-04-19 16:41:15 +0200 |
|---|---|---|
| committer | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2023-05-22 10:14:16 +0300 |
| commit | c95771905c494aa5c2abbb56b3e2f7d4aa3b34f9 (patch) | |
| tree | cee1540f0190c61507692f20fc33e0454f9a0b0b /drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | |
| parent | 95a808328e9918e5716610313f6aec7600108ede (diff) | |
| download | linux-stable-c95771905c494aa5c2abbb56b3e2f7d4aa3b34f9.tar.gz linux-stable-c95771905c494aa5c2abbb56b3e2f7d4aa3b34f9.tar.bz2 linux-stable-c95771905c494aa5c2abbb56b3e2f7d4aa3b34f9.zip | |
drm/msm/dpu: fix cursor block register bit offset in msm8998 hw catalog
This matches the value for both fbdev and sde implementations in the
downstream msm-4.4 repository.
Signed-off-by: Arnaud Vrac <avrac@freebox.fr>
Fixes: 94391a14fc27 ("drm/msm/dpu1: Add MSM8998 to hw catalog")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/532899/
Link: https://lore.kernel.org/r/20230419-dpu-tweaks-v1-8-d1bac46db075@freebox.fr
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h')
| -rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index bdcd554fc8a8..911612952779 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -39,8 +39,8 @@ static const struct dpu_mdp_cfg msm8998_mdp[] = { .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 }, - .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 15 }, - .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 15 }, + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 }, + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 16 }, }, }; |