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author | Jeykumar Sankaran <jsanka@codeaurora.org> | 2018-09-05 19:08:10 -0700 |
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committer | Rob Clark <robdclark@gmail.com> | 2018-10-03 20:24:50 -0400 |
commit | ad8e5c2d7729e2a6f0b5ce3c0e90ab68c40156b8 (patch) | |
tree | 140dd03d7d61a181340ffdfcaedeaa139135f895 /drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | |
parent | d270bdf41e4ac05f16c53482a5769819b040806f (diff) | |
download | linux-stable-ad8e5c2d7729e2a6f0b5ce3c0e90ab68c40156b8.tar.gz linux-stable-ad8e5c2d7729e2a6f0b5ce3c0e90ab68c40156b8.tar.bz2 linux-stable-ad8e5c2d7729e2a6f0b5ce3c0e90ab68c40156b8.zip |
drm/msm/dpu: remove debugfs support for misr
MISR support is the debug feature present in Snapdragon chipsets.
At the layer mixer and interfaces, MISR algorithm can generate CRC
signatures of the pixel data which can be used for validating
the frames generated. Since there are no clients for this feature,
strip down the support from the driver.
changes in v4:
- changed introduced in the series
changes in v5:
- update commit text with the need for the change(Sean)
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h')
-rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h index a89679160237..53484b15403c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -156,9 +156,6 @@ struct dpu_crtc_frame_event { * @event_thread : Pointer to event handler thread * @event_worker : Event worker queue * @event_lock : Spinlock around event handling code - * @misr_enable : boolean entry indicates misr enable/disable status. - * @misr_frame_count : misr frame count provided by client - * @misr_data : store misr data before turning off the clocks. * @phandle: Pointer to power handler * @power_event : registered power event handle * @cur_perf : current performance committed to clock/bandwidth driver @@ -206,9 +203,6 @@ struct dpu_crtc { /* for handling internal event thread */ spinlock_t event_lock; - bool misr_enable; - u32 misr_frame_count; - u32 misr_data[CRTC_DUAL_MIXERS]; struct dpu_power_handle *phandle; struct dpu_power_event *power_event; |