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| author | Jeykumar Sankaran <jsanka@codeaurora.org> | 2018-09-05 19:08:10 -0700 |
|---|---|---|
| committer | Rob Clark <robdclark@gmail.com> | 2018-10-03 20:24:50 -0400 |
| commit | ad8e5c2d7729e2a6f0b5ce3c0e90ab68c40156b8 (patch) | |
| tree | 140dd03d7d61a181340ffdfcaedeaa139135f895 /drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | |
| parent | d270bdf41e4ac05f16c53482a5769819b040806f (diff) | |
| download | linux-stable-ad8e5c2d7729e2a6f0b5ce3c0e90ab68c40156b8.tar.gz linux-stable-ad8e5c2d7729e2a6f0b5ce3c0e90ab68c40156b8.tar.bz2 linux-stable-ad8e5c2d7729e2a6f0b5ce3c0e90ab68c40156b8.zip | |
drm/msm/dpu: remove debugfs support for misr
MISR support is the debug feature present in Snapdragon chipsets.
At the layer mixer and interfaces, MISR algorithm can generate CRC
signatures of the pixel data which can be used for validating
the frames generated. Since there are no clients for this feature,
strip down the support from the driver.
changes in v4:
- changed introduced in the series
changes in v5:
- update commit text with the need for the change(Sean)
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h')
| -rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index c7df8aad6613..b3917e0051cb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -114,8 +114,6 @@ struct dpu_encoder_virt_ops { * @handle_post_kickoff: Do any work necessary post-kickoff work * @trigger_start: Process start event on physical encoder * @needs_single_flush: Whether encoder slaves need to be flushed - * @setup_misr: Sets up MISR, enable and disables based on sysfs - * @collect_misr: Collects MISR data on frame update * @hw_reset: Issue HW recovery such as CTL reset and clear * DPU_ENC_ERR_NEEDS_HW_RESET state * @irq_control: Handler to enable/disable all the encoder IRQs @@ -154,10 +152,6 @@ struct dpu_encoder_phys_ops { void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc); void (*trigger_start)(struct dpu_encoder_phys *phys_enc); bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc); - - void (*setup_misr)(struct dpu_encoder_phys *phys_encs, - bool enable, u32 frame_count); - u32 (*collect_misr)(struct dpu_encoder_phys *phys_enc); void (*hw_reset)(struct dpu_encoder_phys *phys_enc); void (*irq_control)(struct dpu_encoder_phys *phys, bool enable); void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc); |