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| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2023-07-29 00:33:20 +0300 |
|---|---|---|
| committer | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2023-08-02 12:37:53 +0300 |
| commit | 7b4a727e84f094aa3132ddbb4a4e8e435cb03e4b (patch) | |
| tree | d00d8c74c3a47aa9c9e8318699934c61b47cb872 /drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | |
| parent | 1613c5fddd424a5d18b97d21bb2ede608133e205 (diff) | |
| download | linux-stable-7b4a727e84f094aa3132ddbb4a4e8e435cb03e4b.tar.gz linux-stable-7b4a727e84f094aa3132ddbb4a4e8e435cb03e4b.tar.bz2 linux-stable-7b4a727e84f094aa3132ddbb4a4e8e435cb03e4b.zip | |
drm/msm/dpu: drop BWC features from DPU_MDP_foo namespace
The feature bits DPU_MDP_BWC, DPU_MDP_UBWC_1_0, and DPU_MDP_UBWC_1_5 are
not used by the driver, drop them completely.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/550056/
Link: https://lore.kernel.org/r/20230728213320.97309-8-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h')
| -rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 0989aaa9803d..6c9634209e9f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -32,10 +32,6 @@ * MDP TOP BLOCK features * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be done per pipe * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats - * @DPU_MDP_BWC, MDSS HW supports Bandwidth compression. - * @DPU_MDP_UBWC_1_0, This chipsets supports Universal Bandwidth - * compression initial revision - * @DPU_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5 * @DPU_MDP_PERIPH_0_REMOVED Indicates that access to periph top0 block results * in a failure * @DPU_MDP_VSYNC_SEL Enables vsync source selection via MDP_VSYNC_SEL register @@ -46,9 +42,6 @@ enum { DPU_MDP_PANIC_PER_PIPE = 0x1, DPU_MDP_10BIT_SUPPORT, - DPU_MDP_BWC, - DPU_MDP_UBWC_1_0, - DPU_MDP_UBWC_1_5, DPU_MDP_AUDIO_SELECT, DPU_MDP_PERIPH_0_REMOVED, DPU_MDP_VSYNC_SEL, |