diff options
| author | Abhinav Kumar <quic_abhinavk@quicinc.com> | 2022-04-26 07:41:25 -0700 |
|---|---|---|
| committer | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2022-05-02 02:13:00 +0300 |
| commit | 6d084806c8c107dc0b652d6792c7aea9b6b0d66f (patch) | |
| tree | 93eeeb23dd716ed520ef88289a04b4735de031a1 /drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | |
| parent | 25a29653aec65e0b4368ef50921075b1c2da577e (diff) | |
| download | linux-stable-6d084806c8c107dc0b652d6792c7aea9b6b0d66f.tar.gz linux-stable-6d084806c8c107dc0b652d6792c7aea9b6b0d66f.tar.bz2 linux-stable-6d084806c8c107dc0b652d6792c7aea9b6b0d66f.zip | |
drm/msm/dpu: add changes to support writeback in hw_ctl
Add changes to support writeback module in the dpu_hw_ctl
interface.
changes in v4:
- fix the copyright year order
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/483507/
Link: https://lore.kernel.org/r/1650984096-9964-9-git-send-email-quic_abhinavk@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h')
| -rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h index c61a8fddf93c..5755307089b5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _DPU_HW_CTL_H @@ -44,6 +45,7 @@ struct dpu_hw_stage_cfg { */ struct dpu_hw_intf_cfg { enum dpu_intf intf; + enum dpu_wb wb; enum dpu_3d_blend_mode mode_3d; enum dpu_merge_3d merge_3d; enum dpu_ctl_mode_sel intf_mode_sel; @@ -102,6 +104,15 @@ struct dpu_hw_ctl_ops { u32 flushbits); /** + * OR in the given flushbits to the cached pending_(wb_)flush_mask + * No effect on hardware + * @ctx : ctl path ctx pointer + * @blk : writeback block index + */ + void (*update_pending_flush_wb)(struct dpu_hw_ctl *ctx, + enum dpu_wb blk); + + /** * OR in the given flushbits to the cached pending_(intf_)flush_mask * No effect on hardware * @ctx : ctl path ctx pointer @@ -199,6 +210,7 @@ struct dpu_hw_ctl_ops { * @mixer_hw_caps: mixer hardware capabilities * @pending_flush_mask: storage for pending ctl_flush managed via ops * @pending_intf_flush_mask: pending INTF flush + * @pending_wb_flush_mask: pending WB flush * @ops: operation list */ struct dpu_hw_ctl { @@ -212,6 +224,7 @@ struct dpu_hw_ctl { const struct dpu_lm_cfg *mixer_hw_caps; u32 pending_flush_mask; u32 pending_intf_flush_mask; + u32 pending_wb_flush_mask; u32 pending_merge_3d_flush_mask; /* ops */ |