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| author | Marijn Suijten <marijn.suijten@somainline.org> | 2023-04-27 00:37:32 +0200 |
|---|---|---|
| committer | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2023-05-22 10:14:18 +0300 |
| commit | ec6e9b673ad56d019716298c15901d3a46e65c77 (patch) | |
| tree | 39e339d70acbbdc8ce29b1b51f8d7cd8bfd75db6 /drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | |
| parent | a38a9949a96399ecbe213837b2341babe3262423 (diff) | |
| download | linux-stable-ec6e9b673ad56d019716298c15901d3a46e65c77.tar.gz linux-stable-ec6e9b673ad56d019716298c15901d3a46e65c77.tar.bz2 linux-stable-ec6e9b673ad56d019716298c15901d3a46e65c77.zip | |
drm/msm/dpu: Describe TEAR interrupt registers for DSI interfaces
All SoCs since DPU 5.0.0 have the tear interrupt registers moved out of
the PINGPONG block and into the INTF block. Wire up the IRQ register
masks in the interrupt table for enabling, reading and clearing them.
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/534244/
Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-18-27ce1a5ab5c6@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h')
| -rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h index bbf475a1cb45..1f2dabc54c22 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h @@ -23,11 +23,15 @@ enum dpu_hw_intr_reg { MDP_INTF3_INTR, MDP_INTF4_INTR, MDP_INTF5_INTR, + MDP_INTF1_TEAR_INTR, + MDP_INTF2_TEAR_INTR, MDP_AD4_0_INTR, MDP_AD4_1_INTR, MDP_INTF0_7xxx_INTR, MDP_INTF1_7xxx_INTR, + MDP_INTF1_7xxx_TEAR_INTR, MDP_INTF2_7xxx_INTR, + MDP_INTF2_7xxx_TEAR_INTR, MDP_INTF3_7xxx_INTR, MDP_INTF4_7xxx_INTR, MDP_INTF5_7xxx_INTR, |