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authorLinus Torvalds <torvalds@linux-foundation.org>2013-05-21 08:50:57 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2013-05-21 08:50:57 -0700
commit0ddaa974258a4cde9a06c079bfd7863644e10d31 (patch)
treed0b70cb3f82399cb0c48e3c74d3b76639c624290 /drivers/gpu/drm/radeon/radeon_bios.c
parent007b703b3ed74e9af9c0576e7698ccda0170d370 (diff)
parentcc3e06a57d4314ca0582fcf7d6b56dea5ca11f77 (diff)
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Merge branch 'drm-radeon-sun-hainan' of git://people.freedesktop.org/~airlied/linux
Pull radeon sun/hainan support from Dave Airlie: "Since I know its outside the merge window, but since this is new hw I thought I'd try and provoke the new hw exception, it just fills in the blanks in the driver for the new AMD sun and hainan chipsets." * 'drm-radeon-sun-hainan' of git://people.freedesktop.org/~airlied/linux: drm/radeon: add Hainan pci ids drm/radeon: add golden register settings for Hainan (v2) drm/radeon: sun/hainan chips do not have UVD (v2) drm/radeon: track which asics have UVD drm/radeon: radeon-asic updates for Hainan drm/radeon: fill in ucode loading support for Hainan drm/radeon: don't touch DCE or VGA regs on Hainan (v3) drm/radeon: fill in GPU init for Hainan (v2) drm/radeon: add chip family for Hainan
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_bios.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_bios.c28
1 files changed, 16 insertions, 12 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
index fa3c56fba294..061b227dae0c 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -244,24 +244,28 @@ static bool ni_read_disabled_bios(struct radeon_device *rdev)
/* enable the rom */
WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
- /* Disable VGA mode */
- WREG32(AVIVO_D1VGA_CONTROL,
- (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
- AVIVO_DVGA_CONTROL_TIMING_SELECT)));
- WREG32(AVIVO_D2VGA_CONTROL,
- (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
- AVIVO_DVGA_CONTROL_TIMING_SELECT)));
- WREG32(AVIVO_VGA_RENDER_CONTROL,
- (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
+ if (!ASIC_IS_NODCE(rdev)) {
+ /* Disable VGA mode */
+ WREG32(AVIVO_D1VGA_CONTROL,
+ (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
+ AVIVO_DVGA_CONTROL_TIMING_SELECT)));
+ WREG32(AVIVO_D2VGA_CONTROL,
+ (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
+ AVIVO_DVGA_CONTROL_TIMING_SELECT)));
+ WREG32(AVIVO_VGA_RENDER_CONTROL,
+ (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
+ }
WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
r = radeon_read_bios(rdev);
/* restore regs */
WREG32(R600_BUS_CNTL, bus_cntl);
- WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
- WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
- WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
+ if (!ASIC_IS_NODCE(rdev)) {
+ WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
+ WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
+ WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
+ }
WREG32(R600_ROM_CNTL, rom_cntl);
return r;
}