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| author | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2015-09-07 17:34:26 +0300 |
|---|---|---|
| committer | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2016-02-23 09:34:29 +0200 |
| commit | 2427b3037710d4aa71c9c1cdfcd542805e0c53f3 (patch) | |
| tree | 810b6fb9005f3471e65acbace0453f10a4faf1da /drivers/gpu/drm/rcar-du/rcar_du_group.c | |
| parent | a5e18b2b7d5d9486c27142f0a76565954160ab3b (diff) | |
| download | linux-stable-2427b3037710d4aa71c9c1cdfcd542805e0c53f3.tar.gz linux-stable-2427b3037710d4aa71c9c1cdfcd542805e0c53f3.tar.bz2 linux-stable-2427b3037710d4aa71c9c1cdfcd542805e0c53f3.zip | |
drm: rcar-du: Add R8A7795 device support
Document the R8A7795-specific DT bindings and support them in the
driver. The HDMI and LVDS outputs are currently not supported.
Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Diffstat (limited to 'drivers/gpu/drm/rcar-du/rcar_du_group.c')
| -rw-r--r-- | drivers/gpu/drm/rcar-du/rcar_du_group.c | 50 |
1 files changed, 36 insertions, 14 deletions
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c index 144d1e0a7a4a..33b2fc53da3e 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c @@ -1,7 +1,7 @@ /* * rcar_du_group.c -- R-Car Display Unit Channels Pair * - * Copyright (C) 2013-2014 Renesas Electronics Corporation + * Copyright (C) 2013-2015 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) * @@ -56,17 +56,32 @@ static void rcar_du_group_setup_pins(struct rcar_du_group *rgrp) static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp) { - u32 defr8 = DEFR8_CODE | DEFR8_DEFE8; + struct rcar_du_device *rcdu = rgrp->dev; + unsigned int possible_crtcs = + rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs; + u32 defr8 = DEFR8_CODE; - /* The DEFR8 register for the first group also controls RGB output - * routing to DPAD0 and VSPD1 routing to DU0/1/2 for DU instances that - * support it. - */ - if (rgrp->index == 0) { - if (rgrp->dev->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs > 1) - defr8 |= DEFR8_DRGBS_DU(rgrp->dev->dpad0_source); - if (rgrp->dev->vspd1_sink == 2) - defr8 |= DEFR8_VSCS; + if (rcdu->info->gen < 3) { + defr8 |= DEFR8_DEFE8; + + /* On Gen2 the DEFR8 register for the first group also controls + * RGB output routing to DPAD0 and VSPD1 routing to DU0/1/2 for + * DU instances that support it. + */ + if (rgrp->index == 0) { + if (possible_crtcs > 1) + defr8 |= DEFR8_DRGBS_DU(rcdu->dpad0_source); + if (rgrp->dev->vspd1_sink == 2) + defr8 |= DEFR8_VSCS; + } + } else { + /* On Gen3 VSPD routing can't be configured, but DPAD routing + * needs to be set despite having a single option available. + */ + u32 crtc = ffs(possible_crtcs) - 1; + + if (crtc / 2 == rgrp->index) + defr8 |= DEFR8_DRGBS_DU(crtc); } rcar_du_group_write(rgrp, DEFR8, defr8); @@ -74,11 +89,15 @@ static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp) static void rcar_du_group_setup(struct rcar_du_group *rgrp) { + struct rcar_du_device *rcdu = rgrp->dev; + /* Enable extended features */ rcar_du_group_write(rgrp, DEFR, DEFR_CODE | DEFR_DEFE); - rcar_du_group_write(rgrp, DEFR2, DEFR2_CODE | DEFR2_DEFE2G); - rcar_du_group_write(rgrp, DEFR3, DEFR3_CODE | DEFR3_DEFE3); - rcar_du_group_write(rgrp, DEFR4, DEFR4_CODE); + if (rcdu->info->gen < 3) { + rcar_du_group_write(rgrp, DEFR2, DEFR2_CODE | DEFR2_DEFE2G); + rcar_du_group_write(rgrp, DEFR3, DEFR3_CODE | DEFR3_DEFE3); + rcar_du_group_write(rgrp, DEFR4, DEFR4_CODE); + } rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5); rcar_du_group_setup_pins(rgrp); @@ -98,6 +117,9 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp) DIDSR_PDCS_CLK(0, 0)); } + if (rcdu->info->gen >= 3) + rcar_du_group_write(rgrp, DEFR10, DEFR10_CODE | DEFR10_DEFE10); + /* Use DS1PR and DS2PR to configure planes priorities and connects the * superposition 0 to DU0 pins. DU1 pins will be configured dynamically. */ |