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| author | Dave Stevenson <dave.stevenson@raspberrypi.com> | 2022-06-13 16:47:39 +0200 |
|---|---|---|
| committer | Maxime Ripard <maxime@cerno.tech> | 2022-06-28 14:55:26 +0200 |
| commit | 3b45eee87da171caa28f61240ddb5c21170cda53 (patch) | |
| tree | caf23a14a2c5d7bd3f3f682cb267715f19d17c5d /drivers/gpu/drm/vc4 | |
| parent | 89c4bbe2a01ea401c2b0fabc104720809084b77f (diff) | |
| download | linux-stable-3b45eee87da171caa28f61240ddb5c21170cda53.tar.gz linux-stable-3b45eee87da171caa28f61240ddb5c21170cda53.tar.bz2 linux-stable-3b45eee87da171caa28f61240ddb5c21170cda53.zip | |
drm/vc4: dsi: Correct DSI divider calculations
The divider calculations tried to find the divider just faster than the
clock requested. However if it required a divider of 7 then the for loop
aborted without handling the "error" case, and could end up with a clock
lower than requested.
The integer divider from parent PLL to DSI clock is also capable of
going up to /255, not just /7 that the driver was trying. This allows
for slower link frequencies on the DSI bus where the resolution permits.
Correct the loop so that we always have a clock greater than requested,
and covering the whole range of dividers.
Fixes: 86c1b9eff3f2 ("drm/vc4: Adjust modes in DSI to work around the integer PLL divider.")
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://lore.kernel.org/r/20220613144800.326124-13-maxime@cerno.tech
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Diffstat (limited to 'drivers/gpu/drm/vc4')
| -rw-r--r-- | drivers/gpu/drm/vc4/vc4_dsi.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/gpu/drm/vc4/vc4_dsi.c index e82ee94cafc7..81a6c4e9576d 100644 --- a/drivers/gpu/drm/vc4/vc4_dsi.c +++ b/drivers/gpu/drm/vc4/vc4_dsi.c @@ -805,11 +805,9 @@ static bool vc4_dsi_encoder_mode_fixup(struct drm_encoder *encoder, /* Find what divider gets us a faster clock than the requested * pixel clock. */ - for (divider = 1; divider < 8; divider++) { - if (parent_rate / divider < pll_clock) { - divider--; + for (divider = 1; divider < 255; divider++) { + if (parent_rate / (divider + 1) < pll_clock) break; - } } /* Now that we've picked a PLL divider, calculate back to its |