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| author | Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> | 2024-04-08 22:35:40 +0530 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2024-04-09 14:21:52 -0700 |
| commit | b5c2ca0372dcf5bb7403032ca609c9df1fb23bfc (patch) | |
| tree | ae736b45d4a5b960d4ab4f67529168534097324c /drivers/gpu/drm/xe/regs/xe_gt_regs.h | |
| parent | 183620f9ae3c8ebd9e126e07020b235d34547eb4 (diff) | |
| download | linux-stable-b5c2ca0372dcf5bb7403032ca609c9df1fb23bfc.tar.gz linux-stable-b5c2ca0372dcf5bb7403032ca609c9df1fb23bfc.tar.bz2 linux-stable-b5c2ca0372dcf5bb7403032ca609c9df1fb23bfc.zip | |
drm/xe/xe2hpg: Determine flat ccs offset for vram
on Xe2 dgfx platform determine the offset using Flat CCS size
bitfield of XE2_FLAT_CCS_BASE_RANGE_[UPPER/LOWER] mcr registers.
v2: function argument tile_size changed from pass by reference to pass
by value
Bspec: 68023
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Signed-off-by: Akshata Jahagirdar <akshata.jahagirdar@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240408170545.3769566-7-balasubramani.vivekanandan@intel.com
Diffstat (limited to 'drivers/gpu/drm/xe/regs/xe_gt_regs.h')
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index 6617c86a096b..d404f211bc36 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -69,6 +69,7 @@ #define XEHP_TILE_ADDR_RANGE(_idx) XE_REG_MCR(0x4900 + (_idx) * 4) #define XEHP_FLAT_CCS_BASE_ADDR XE_REG_MCR(0x4910) +#define XEHP_FLAT_CCS_PTR REG_GENMASK(31, 8) #define WM_CHICKEN3 XE_REG_MCR(0x5588, XE_REG_OPTION_MASKED) #define HIZ_PLANE_COMPRESSION_DIS REG_BIT(10) @@ -142,6 +143,10 @@ #define XE2_FLAT_CCS_BASE_RANGE_LOWER XE_REG_MCR(0x8800) #define XE2_FLAT_CCS_ENABLE REG_BIT(0) +#define XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK REG_GENMASK(31, 6) + +#define XE2_FLAT_CCS_BASE_RANGE_UPPER XE_REG_MCR(0x8804) +#define XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK REG_GENMASK(7, 0) #define GSCPSMI_BASE XE_REG(0x880c) |