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| author | Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> | 2023-08-17 13:18:29 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 11:40:21 -0500 |
| commit | f4c33ae8eca2fa459d0d58baa1a26234598e6b32 (patch) | |
| tree | 6bf8aa60d6b8ac11ee56d4714cd4681d3e617f37 /drivers/gpu/drm/xe/regs/xe_gt_regs.h | |
| parent | aef61349ef1bf01badfa3ea955ba84048467f691 (diff) | |
| download | linux-stable-f4c33ae8eca2fa459d0d58baa1a26234598e6b32.tar.gz linux-stable-f4c33ae8eca2fa459d0d58baa1a26234598e6b32.tar.bz2 linux-stable-f4c33ae8eca2fa459d0d58baa1a26234598e6b32.zip | |
drm/xe: GSC forcewake support
The ID for the GSC forcewake domain already exists, but we're missing
the register definitions and the domain intialization, so add that in.
v2: move reg definition to be in address order (Matt)
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230817201831.1583172-6-daniele.ceraolospurio@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/regs/xe_gt_regs.h')
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index b6e870302cc7..51d59e1229be 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -39,6 +39,7 @@ #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14) #define GMD_ID_REVID REG_GENMASK(5, 0) +#define FORCEWAKE_ACK_GSC XE_REG(0xdf8) #define FORCEWAKE_ACK_GT_MTL XE_REG(0xdfc) /* L3 Cache Control */ @@ -256,6 +257,7 @@ #define FORCEWAKE_RENDER XE_REG(0xa278) #define FORCEWAKE_MEDIA_VDBOX(n) XE_REG(0xa540 + (n) * 4) #define FORCEWAKE_MEDIA_VEBOX(n) XE_REG(0xa560 + (n) * 4) +#define FORCEWAKE_GSC XE_REG(0xa618) #define XEHPC_LNCFMISCCFGREG0 XE_REG_MCR(0xb01c, XE_REG_OPTION_MASKED) #define XEHPC_OVRLSCCC REG_BIT(0) |