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| author | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-04-27 15:32:49 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-19 18:32:21 -0500 |
| commit | 5f230a144a33d9a33448063a23d65c53b6d84cea (patch) | |
| tree | 5d1c6fad6fe896b174cdb3f7ac8eb95ee4e611ba /drivers/gpu/drm/xe/xe_gt_clock.c | |
| parent | d9b79ad275e7a98c566b3ac4b32950142d6bf9ad (diff) | |
| download | linux-stable-5f230a144a33d9a33448063a23d65c53b6d84cea.tar.gz linux-stable-5f230a144a33d9a33448063a23d65c53b6d84cea.tar.bz2 linux-stable-5f230a144a33d9a33448063a23d65c53b6d84cea.zip | |
drm/xe: Use REG_FIELD/REG_BIT for all regs/*.h
Convert the macro declarations to the equivalent GENMASK and
and bitfield prep for all registers.
v2 (Matt Roper):
- Fix wrong conversion of RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK
- Reorder fields of XEHP_SLICE_UNIT_LEVEL_CLKGATE for consistency
- Simplify CTC_SOURCE_* by only defining CTC_SOURCE_DIVIDE_LOGIC
as REG_BIT(0)
v3: Also remove DOP_CLOCK_GATE_ENABLE that is unused and wrongly defined
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://lore.kernel.org/r/20230427223256.1432787-4-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_gt_clock.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_gt_clock.c | 19 |
1 files changed, 8 insertions, 11 deletions
diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c index 1b7d00284535..49625d49bdcc 100644 --- a/drivers/gpu/drm/xe/xe_gt_clock.c +++ b/drivers/gpu/drm/xe/xe_gt_clock.c @@ -17,13 +17,12 @@ static u32 read_reference_ts_freq(struct xe_gt *gt) u32 ts_override = xe_mmio_read32(gt, TIMESTAMP_OVERRIDE.reg); u32 base_freq, frac_freq; - base_freq = ((ts_override & TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >> - TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1; + base_freq = REG_FIELD_GET(TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK, + ts_override) + 1; base_freq *= 1000000; - frac_freq = ((ts_override & - TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >> - TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT); + frac_freq = REG_FIELD_GET(TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK, + ts_override); frac_freq = 1000000 / (frac_freq + 1); return base_freq + frac_freq; @@ -35,9 +34,8 @@ static u32 get_crystal_clock_freq(u32 rpm_config_reg) const u32 f24_mhz = 24000000; const u32 f25_mhz = 25000000; const u32 f38_4_mhz = 38400000; - u32 crystal_clock = - (rpm_config_reg & RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >> - RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; + u32 crystal_clock = REG_FIELD_GET(RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, + rpm_config_reg); switch (crystal_clock) { case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ : @@ -62,7 +60,7 @@ int xe_gt_clock_init(struct xe_gt *gt) /* Assuming gen11+ so assert this assumption is correct */ XE_BUG_ON(GRAPHICS_VER(gt_to_xe(gt)) < 11); - if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { + if (ctc_reg & CTC_SOURCE_DIVIDE_LOGIC) { freq = read_reference_ts_freq(gt); } else { u32 c0 = xe_mmio_read32(gt, RPM_CONFIG0.reg); @@ -74,8 +72,7 @@ int xe_gt_clock_init(struct xe_gt *gt) * register increments from this frequency (it might * increment only every few clock cycle). */ - freq >>= 3 - ((c0 & RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> - RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT); + freq >>= 3 - REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, c0); } gt->info.clock_freq = freq; |