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| author | Fei Yang <fei.yang@intel.com> | 2023-11-22 12:45:01 -0800 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 11:45:07 -0500 |
| commit | 473b62763b76e8bb0793ac5f030779c43ecd79e6 (patch) | |
| tree | e0be94db482536a1bdb8957b81723e18249bfae0 /drivers/gpu/drm/xe/xe_uc_fw.c | |
| parent | e1fbc4f18d5b4405271e964670b9b054c4397127 (diff) | |
| download | linux-stable-473b62763b76e8bb0793ac5f030779c43ecd79e6.tar.gz linux-stable-473b62763b76e8bb0793ac5f030779c43ecd79e6.tar.bz2 linux-stable-473b62763b76e8bb0793ac5f030779c43ecd79e6.zip | |
drm/xe: explicitly set GGTT access for GuC DMA
Confirmed with hardware that setting GGTT memory access for GuC
firmware loading is correct for all platforms and required for
new platforms going forward.
Signed-off-by: Fei Yang <fei.yang@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20231122204501.1353325-2-fei.yang@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_uc_fw.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_uc_fw.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c index 2fcec528a1d1..e806e7b6ae42 100644 --- a/drivers/gpu/drm/xe/xe_uc_fw.c +++ b/drivers/gpu/drm/xe/xe_uc_fw.c @@ -746,7 +746,8 @@ static int uc_fw_xfer(struct xe_uc_fw *uc_fw, u32 offset, u32 dma_flags) /* Set the source address for the uCode */ src_offset = uc_fw_ggtt_offset(uc_fw) + uc_fw->css_offset; xe_mmio_write32(gt, DMA_ADDR_0_LOW, lower_32_bits(src_offset)); - xe_mmio_write32(gt, DMA_ADDR_0_HIGH, upper_32_bits(src_offset)); + xe_mmio_write32(gt, DMA_ADDR_0_HIGH, + upper_32_bits(src_offset) | DMA_ADDRESS_SPACE_GGTT); /* Set the DMA destination */ xe_mmio_write32(gt, DMA_ADDR_1_LOW, offset); |