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author | Christian König <christian.koenig@amd.com> | 2020-01-31 14:58:05 +0100 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2020-05-06 16:50:40 -0400 |
commit | 9d11eb0d0c4659c6414b22d86b7f8813e254dcba (patch) | |
tree | b4abba8e7f9006619c50d24281ba4273a208a5fb /drivers/gpu/drm | |
parent | 85d4d684feccc200ee2c93fe06a563bb70a6fb20 (diff) | |
download | linux-stable-9d11eb0d0c4659c6414b22d86b7f8813e254dcba.tar.gz linux-stable-9d11eb0d0c4659c6414b22d86b7f8813e254dcba.tar.bz2 linux-stable-9d11eb0d0c4659c6414b22d86b7f8813e254dcba.zip |
drm/amdgpu: use the BAR if possible in amdgpu_device_vram_access v2
This should speed up debugging VRAM access a lot.
v2: add HDP flush/invalidate
Unrevert: RAS issue at root of the issue has been addressed
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Jonathan Kim <Jonathan.Kim@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Kent Russell <kent.russell@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index caa38e7d502e..bf302c799832 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -255,6 +255,32 @@ void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, uint32_t hi = ~0; uint64_t last; + +#ifdef CONFIG_64BIT + last = min(pos + size, adev->gmc.visible_vram_size); + if (last > pos) { + void __iomem *addr = adev->mman.aper_base_kaddr + pos; + size_t count = last - pos; + + if (write) { + memcpy_toio(addr, buf, count); + mb(); + amdgpu_asic_flush_hdp(adev, NULL); + } else { + amdgpu_asic_invalidate_hdp(adev, NULL); + mb(); + memcpy_fromio(buf, addr, count); + } + + if (count == size) + return; + + pos += count; + buf += count / 4; + size -= count; + } +#endif + spin_lock_irqsave(&adev->mmio_idx_lock, flags); for (last = pos + size; pos < last; pos += 4) { uint32_t tmp = pos >> 31; |