diff options
author | Alvin Lee <Alvin.Lee2@amd.com> | 2023-03-13 12:54:49 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2023-03-31 11:18:53 -0400 |
commit | ac18b610fd95762125cd6a7194cc7e2e3b94e3ed (patch) | |
tree | 5f3eaa8fd98016d34b30ae72a6f6be141a3f1377 /drivers/gpu/drm | |
parent | d29fb7baab09b6a1dc484c9c67933253883e770a (diff) | |
download | linux-stable-ac18b610fd95762125cd6a7194cc7e2e3b94e3ed.tar.gz linux-stable-ac18b610fd95762125cd6a7194cc7e2e3b94e3ed.tar.bz2 linux-stable-ac18b610fd95762125cd6a7194cc7e2e3b94e3ed.zip |
drm/amd/display: Enable FPO for configs that could reduce vlevel
[Description]
- On high refresh rate DRR displays that support VBLANK naturally,
UCLK could be idling at DPM1 instead of DPM0 since it doesn't use
FPO
- To achieve DPM0, enable FPO on these configs even though it can
support P-State without FPO
- Default disable for now, have debug option to enable
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm')
4 files changed, 20 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 475128db02bb..2d2621abf012 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -873,6 +873,7 @@ struct dc_debug_options { bool dig_fifo_off_in_blank; bool temp_mst_deallocation_sequence; bool override_dispclk_programming; + bool disable_fpo_optimizations; }; struct gpu_info_soc_bounding_box_v1_0; diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c index 1715909b1225..b8c1de357e5f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c @@ -725,6 +725,7 @@ static const struct dc_debug_options debug_defaults_drv = { .min_prefetch_in_strobe_ns = 60000, // 60us .disable_unbounded_requesting = false, .override_dispclk_programming = true, + .disable_fpo_optimizations = true, }; static const struct dc_debug_options debug_defaults_diags = { diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c index c6a0e84885a2..5e0b1484dc18 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c @@ -723,6 +723,7 @@ static const struct dc_debug_options debug_defaults_drv = { .min_prefetch_in_strobe_ns = 60000, // 60us .disable_unbounded_requesting = false, .override_dispclk_programming = true, + .disable_fpo_optimizations = true, }; static const struct dc_debug_options debug_defaults_diags = { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c index 6b29d3a9520f..4e17f2c8d2b7 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c @@ -1961,7 +1961,8 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; - if (!pstate_en) { + if (!pstate_en || (!dc->debug.disable_fpo_optimizations && + pstate_en && vlevel != 0)) { /* only when the mclk switch can not be natural, is the fw based vblank stretch attempted */ context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(dc, context); @@ -1985,11 +1986,21 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; } - dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false); - maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; - dcfclk_from_fw_based_mclk_switching = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; - pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != - dm_dram_clock_change_unsupported; + dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel_temp, false); + if (vlevel_temp < vlevel) { + vlevel = vlevel_temp; + maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; + dcfclk_from_fw_based_mclk_switching = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; + pstate_en = true; + } else { + /* Restore FCLK latency and re-run validation to go back to original validation + * output if we find that enabling FPO does not give us any benefit (i.e. lower + * voltage level) + */ + context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; + context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us; + dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false); + } } } |