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authorKevin Wang <kevin1.wang@amd.com>2019-07-12 14:40:12 +0800
committerAlex Deucher <alexander.deucher@amd.com>2019-07-16 13:03:03 -0500
commiteaf963b5c17e611ca35850f65db7ebe929bef774 (patch)
tree70659ea50cb3fbe8536142bcf9ac3e4499a1a15d /drivers/gpu/drm
parent75ee64875e758b2f10d319a50dc787516c52d3de (diff)
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drm/amd/powerplay: add socclk profile dpm support.
1.miss socclk profile support when bringup. 2.add feature check for socclk. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/amd/powerplay/amdgpu_smu.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 04132653e289..5f844357e6ac 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -149,6 +149,11 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
pr_warn("gfxclk dpm is not enabled\n");
return 0;
}
+ case SMU_SOCCLK:
+ if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
+ pr_warn("sockclk dpm is not enabled\n");
+ return 0;
+ }
break;
default:
break;
@@ -1388,6 +1393,7 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu,
return ret;
smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
+ smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
break;
case AMD_DPM_FORCED_LEVEL_MANUAL: