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| author | Mario Limonciello <mario.limonciello@amd.com> | 2024-02-15 15:48:47 -0600 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-02-16 15:44:30 -0500 |
| commit | 2bb2ad58f6b711edb94fa43e5ac65323532fde95 (patch) | |
| tree | 90c9a45d169d56e0a492b92ce1b2124d02c9aee6 /drivers/gpu | |
| parent | f6aed043ee5d75b3d1bfc452b1a9584b63c8f76b (diff) | |
| download | linux-stable-2bb2ad58f6b711edb94fa43e5ac65323532fde95.tar.gz linux-stable-2bb2ad58f6b711edb94fa43e5ac65323532fde95.tar.bz2 linux-stable-2bb2ad58f6b711edb94fa43e5ac65323532fde95.zip | |
drm/amd: Change `jpeg_v4_0_5_start_dpg_mode()` to void
jpeg_v4_0_5_start_dpg_mode() always returns 0 and the return value
doesn't get used in the caller jpeg_v4_0_5_start(). Modify the
function to be void.
Reported-by: coverity-bot <keescook+coverity-bot@chromium.org>
Addresses-Coverity-ID: 1583635 ("Code maintainability issues")
Fixes: 0a119d53f74a ("drm/amdgpu/jpeg: add support for jpeg DPG mode")
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c index 3602738874ee..8d1754e35605 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c @@ -358,7 +358,7 @@ static int jpeg_v4_0_5_enable_static_power_gating(struct amdgpu_device *adev, in * * Start JPEG block with dpg mode */ -static int jpeg_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) +static void jpeg_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) { struct amdgpu_ring *ring = adev->jpeg.inst[inst_idx].ring_dec; uint32_t reg_data = 0; @@ -411,8 +411,6 @@ static int jpeg_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_CNTL, 0x00000002L); WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_SIZE, ring->ring_size / 4); ring->wptr = RREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR); - - return 0; } /** @@ -458,7 +456,7 @@ static int jpeg_v4_0_5_start(struct amdgpu_device *adev) VCN_JPEG_DB_CTRL__EN_MASK); if (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG) { - r = jpeg_v4_0_5_start_dpg_mode(adev, i, adev->jpeg.indirect_sram); + jpeg_v4_0_5_start_dpg_mode(adev, i, adev->jpeg.indirect_sram); continue; } |