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| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2023-02-12 01:12:19 +0200 |
|---|---|---|
| committer | Abhinav Kumar <quic_abhinavk@quicinc.com> | 2023-03-03 10:04:09 -0800 |
| commit | 38164e990a42ca276f72ab89fd24131e6d73b023 (patch) | |
| tree | 293f6e783d52867a3a1faa21cfc0b80b3cdcbbc9 /drivers/gpu | |
| parent | 03c0c3cb22a4ff29afba1b43f0330289ea80433f (diff) | |
| download | linux-stable-38164e990a42ca276f72ab89fd24131e6d73b023.tar.gz linux-stable-38164e990a42ca276f72ab89fd24131e6d73b023.tar.bz2 linux-stable-38164e990a42ca276f72ab89fd24131e6d73b023.zip | |
drm/msm/dpu: correct sm6115 scaler
QSEED4 is a newer variant of QSEED3LITE, which should be used on
sm6115. Fix the used feature masks.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Fixes: 3581b7062cec ("drm/msm/disp/dpu1: add support for display on SM6115")
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/522219/
Link: https://lore.kernel.org/r/20230211231259.1308718-11-dmitry.baryshkov@linaro.org
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 360ca7b5e507..4a26ef7bb024 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -30,9 +30,6 @@ #define VIG_SC7180_MASK \ (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4)) -#define VIG_SM8250_MASK \ - (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE)) - #define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL)) #define DMA_MSM8998_MASK \ @@ -358,7 +355,7 @@ static const struct dpu_caps sc7180_dpu_caps = { static const struct dpu_caps sm6115_dpu_caps = { .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, .max_mixer_blendstages = 0x4, - .qseed_type = DPU_SSPP_SCALER_QSEED3LITE, + .qseed_type = DPU_SSPP_SCALER_QSEED4, .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ .ubwc_version = DPU_HW_UBWC_VER_10, .has_dim_layer = true, @@ -1235,10 +1232,10 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = { }; static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 = - _VIG_SBLK("0", 2, DPU_SSPP_SCALER_QSEED3LITE); + _VIG_SBLK("0", 2, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_cfg sm6115_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK, + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK, sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), |