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| author | Alex Hung <alex.hung@amd.com> | 2024-02-29 19:50:52 -0700 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-03-20 13:38:12 -0400 |
| commit | 86cbadaea4aa468583acb85bb7f33e69f98bb1c3 (patch) | |
| tree | 1178fe24d81fe3f0f507943775b913a906ba7e5d /drivers/gpu | |
| parent | a63dce3a4ba917a440c8e17de6d808bcea313f7e (diff) | |
| download | linux-stable-86cbadaea4aa468583acb85bb7f33e69f98bb1c3.tar.gz linux-stable-86cbadaea4aa468583acb85bb7f33e69f98bb1c3.tar.bz2 linux-stable-86cbadaea4aa468583acb85bb7f33e69f98bb1c3.zip | |
drm/amd/display: Delete duplicated function prototypes
[Why & How]
dcn32_smu_transfer_wm_table_dram_2_smu is defined twice so one is
removed. Also adjust prototype orders.
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h index c76352a817de..5c44ab0e8667 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h @@ -37,10 +37,9 @@ #define DALSMC_Result_OK 0x1 void dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable); -void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr); -void dcn32_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr); void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways); void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr); +void dcn32_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr); unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz); void dcn32_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable); |