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| author | Aurabindo Pillai <aurabindo.pillai@amd.com> | 2023-02-21 18:35:14 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-02-28 14:30:55 -0500 |
| commit | a03e3cb16dfdf4e39ed4ed80314256f9ba671ff0 (patch) | |
| tree | e9bd0a593a5ce0fb21c5709614d1389078e7f1c1 /drivers/gpu | |
| parent | 32953485c558cecf08f33fbfa251e80e44cef981 (diff) | |
| download | linux-stable-a03e3cb16dfdf4e39ed4ed80314256f9ba671ff0.tar.gz linux-stable-a03e3cb16dfdf4e39ed4ed80314256f9ba671ff0.tar.bz2 linux-stable-a03e3cb16dfdf4e39ed4ed80314256f9ba671ff0.zip | |
drm/amd/display: fix clock sequence logic for DCN32
[Why&How]
The newer commit sequence on DCN32 onwards did not finish clock
optimization sequence since the newer sequence did not end up calling
dc_post_update_surfaces_to_stream() which resets dc->optimized_required.
Call this function before passing control on to the new commit sequence.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc.c | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 65b3c3052628..e3bfc4bb8341 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -4142,24 +4142,30 @@ void dc_commit_updates_for_stream(struct dc *dc, struct dc_context *dc_ctx = dc->ctx; int i, j; + stream_status = dc_stream_get_status(stream); + context = dc->current_state; + + update_type = dc_check_update_surfaces_for_stream( + dc, srf_updates, surface_count, stream_update, stream_status); + /* TODO: Since change commit sequence can have a huge impact, * we decided to only enable it for DCN3x. However, as soon as * we get more confident about this change we'll need to enable * the new sequence for all ASICs. */ if (dc->ctx->dce_version >= DCN_VERSION_3_2) { + /* + * Previous frame finished and HW is ready for optimization. + */ + if (update_type == UPDATE_TYPE_FAST) + dc_post_update_surfaces_to_stream(dc); + dc_update_planes_and_stream(dc, srf_updates, surface_count, stream, stream_update); return; } - stream_status = dc_stream_get_status(stream); - context = dc->current_state; - - update_type = dc_check_update_surfaces_for_stream( - dc, srf_updates, surface_count, stream_update, stream_status); - if (update_type >= update_surface_trace_level) update_surface_trace(dc, srf_updates, surface_count); |