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| author | Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> | 2021-12-09 16:05:36 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-12-30 08:54:44 -0500 |
| commit | c856f16c33e6ed4bcfe3f0e51afeb9b08ac48f0d (patch) | |
| tree | c6d38d40aa0a8bf5b3b24de469c5b904e694b710 /drivers/gpu | |
| parent | 0d988e5de7aa5ee8865cbc664180ae67918a6b19 (diff) | |
| download | linux-stable-c856f16c33e6ed4bcfe3f0e51afeb9b08ac48f0d.tar.gz linux-stable-c856f16c33e6ed4bcfe3f0e51afeb9b08ac48f0d.tar.bz2 linux-stable-c856f16c33e6ed4bcfe3f0e51afeb9b08ac48f0d.zip | |
drm/amd/display: Set optimize_pwr_state for DCN31
[Why]
We'll exit optimized power state to do link detection but we won't enter
back into the optimized power state.
This could potentially block s2idle entry depending on the sequencing,
but it also means we're losing some power during the transition period.
[How]
Hook up the handler like DCN21. It was also missed like the
exit_optimized_pwr_state callback.
Fixes: 64b1d0e8d500 ("drm/amd/display: Add DCN3.1 HWSEQ")
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Eric Yang <Eric.Yang2@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c index 7a7a8c5edabd..d7559e5a99ce 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c @@ -103,6 +103,7 @@ static const struct hw_sequencer_funcs dcn31_funcs = { .z10_restore = dcn31_z10_restore, .z10_save_init = dcn31_z10_save_init, .set_disp_pattern_generator = dcn30_set_disp_pattern_generator, + .optimize_pwr_state = dcn21_optimize_pwr_state, .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state, .update_visual_confirm_color = dcn20_update_visual_confirm_color, }; |