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| author | Lang Cheng <chenglang@huawei.com> | 2021-06-21 16:00:37 +0800 |
|---|---|---|
| committer | Jason Gunthorpe <jgg@nvidia.com> | 2021-06-21 15:03:41 -0300 |
| commit | a762fe656b1d59a3d597c0556aa6c029c569364a (patch) | |
| tree | d3407239b44dd9f85d31a78f6b6ad75fd8e8cf81 /drivers/infiniband/hw | |
| parent | fe331da0f210c60342b042a03fe53f1b564b412b (diff) | |
| download | linux-stable-a762fe656b1d59a3d597c0556aa6c029c569364a.tar.gz linux-stable-a762fe656b1d59a3d597c0556aa6c029c569364a.tar.bz2 linux-stable-a762fe656b1d59a3d597c0556aa6c029c569364a.zip | |
RDMA/hns: Add hr_reg_write_bool()
In order to avoid to do bitwise operations on a boolean value, add a new
register interface to avoid sparse comlaint about "dubious: x & !y" when
calling hr_reg_write(ctx, field, !!val).
Fixes: dc504774408b ("RDMA/hns: Use new interface to set MPT related fields")
Fixes: 495c24808ce7 ("RDMA/hns: Add XRC subtype in QPC and XRC type in SRQC")
Link: https://lore.kernel.org/r/1624262443-24528-4-git-send-email-liweihang@huawei.com
Signed-off-by: Lang Cheng <chenglang@huawei.com>
Signed-off-by: Weihang Li <liweihang@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Diffstat (limited to 'drivers/infiniband/hw')
| -rw-r--r-- | drivers/infiniband/hw/hns/hns_roce_common.h | 8 | ||||
| -rw-r--r-- | drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 24 |
2 files changed, 20 insertions, 12 deletions
diff --git a/drivers/infiniband/hw/hns/hns_roce_common.h b/drivers/infiniband/hw/hns/hns_roce_common.h index 3a5658f117ad..b73e55de83ac 100644 --- a/drivers/infiniband/hw/hns/hns_roce_common.h +++ b/drivers/infiniband/hw/hns/hns_roce_common.h @@ -77,6 +77,14 @@ #define hr_reg_clear(ptr, field) _hr_reg_clear(ptr, field) +#define _hr_reg_write_bool(ptr, field_type, field_h, field_l, val) \ + ({ \ + (val) ? _hr_reg_enable(ptr, field_type, field_h, field_l) : \ + _hr_reg_clear(ptr, field_type, field_h, field_l); \ + }) + +#define hr_reg_write_bool(ptr, field, val) _hr_reg_write_bool(ptr, field, val) + #define _hr_reg_write(ptr, field_type, field_h, field_l, val) \ ({ \ _hr_reg_clear(ptr, field_type, field_h, field_l); \ diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c index 2a4d748980e3..7afecc64b250 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c @@ -3109,16 +3109,16 @@ static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev, hr_reg_write(mpt_entry, MPT_PD, mr->pd); hr_reg_enable(mpt_entry, MPT_L_INV_EN); - hr_reg_write(mpt_entry, MPT_BIND_EN, - !!(mr->access & IB_ACCESS_MW_BIND)); - hr_reg_write(mpt_entry, MPT_ATOMIC_EN, - !!(mr->access & IB_ACCESS_REMOTE_ATOMIC)); - hr_reg_write(mpt_entry, MPT_RR_EN, - !!(mr->access & IB_ACCESS_REMOTE_READ)); - hr_reg_write(mpt_entry, MPT_RW_EN, - !!(mr->access & IB_ACCESS_REMOTE_WRITE)); - hr_reg_write(mpt_entry, MPT_LW_EN, - !!((mr->access & IB_ACCESS_LOCAL_WRITE))); + hr_reg_write_bool(mpt_entry, MPT_BIND_EN, + mr->access & IB_ACCESS_MW_BIND); + hr_reg_write_bool(mpt_entry, MPT_ATOMIC_EN, + mr->access & IB_ACCESS_REMOTE_ATOMIC); + hr_reg_write_bool(mpt_entry, MPT_RR_EN, + mr->access & IB_ACCESS_REMOTE_READ); + hr_reg_write_bool(mpt_entry, MPT_RW_EN, + mr->access & IB_ACCESS_REMOTE_WRITE); + hr_reg_write_bool(mpt_entry, MPT_LW_EN, + mr->access & IB_ACCESS_LOCAL_WRITE); mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); @@ -5718,8 +5718,8 @@ static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf) } hr_reg_write(ctx, SRQC_SRQ_ST, 1); - hr_reg_write(ctx, SRQC_SRQ_TYPE, - !!(srq->ibsrq.srq_type == IB_SRQT_XRC)); + hr_reg_write_bool(ctx, SRQC_SRQ_TYPE, + srq->ibsrq.srq_type == IB_SRQT_XRC); hr_reg_write(ctx, SRQC_PD, to_hr_pd(srq->ibsrq.pd)->pdn); hr_reg_write(ctx, SRQC_SRQN, srq->srqn); hr_reg_write(ctx, SRQC_XRCD, srq->xrcdn); |