diff options
| author | Rob Clark <robdclark@chromium.org> | 2020-11-09 11:47:26 -0700 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2020-11-10 12:25:49 +0000 |
| commit | bffb2eaf0ba2c0bdd7fc2c4e194dab6783f5d8c1 (patch) | |
| tree | 1d43cb88cc0f25f8f946b05ec44e4ee226f7dbab /drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | |
| parent | 5c7469c66f953a2eb223468d7aa40062af9c14ab (diff) | |
| download | linux-stable-bffb2eaf0ba2c0bdd7fc2c4e194dab6783f5d8c1.tar.gz linux-stable-bffb2eaf0ba2c0bdd7fc2c4e194dab6783f5d8c1.tar.bz2 linux-stable-bffb2eaf0ba2c0bdd7fc2c4e194dab6783f5d8c1.zip | |
iommu/arm-smmu: Add a way for implementations to influence SCTLR
For the Adreno GPU's SMMU, we want SCTLR.HUPCF set to ensure that
pending translations are not terminated on iova fault. Otherwise
a terminated CP read could hang the GPU by returning invalid
command-stream data. Add a hook to for the implementation to modify
the sctlr value if it wishes.
Co-developed-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Link: https://lore.kernel.org/r/20201109184728.2463097-3-jcrouse@codeaurora.org
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c')
| -rw-r--r-- | drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index b5384c4d92c8..d0636c803a36 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -20,6 +20,18 @@ static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) return container_of(smmu, struct qcom_smmu, smmu); } +static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx, + u32 reg) +{ + /* + * On the GPU device we want to process subsequent transactions after a + * fault to keep the GPU from hanging + */ + reg |= ARM_SMMU_SCTLR_HUPCF; + + arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); +} + #define QCOM_ADRENO_SMMU_GPU_SID 0 static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) @@ -289,6 +301,7 @@ static const struct arm_smmu_impl qcom_adreno_smmu_impl = { .def_domain_type = qcom_smmu_def_domain_type, .reset = qcom_smmu500_reset, .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank, + .write_sctlr = qcom_adreno_smmu_write_sctlr, }; static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, |