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author | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2022-05-16 15:39:23 +0200 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2022-05-16 15:39:23 +0200 |
commit | d6da35e0c6d50f76eaf11a0496d3d2ec1a1fea3f (patch) | |
tree | c757e3701fbe9dbbf35525e980bd155c244cce52 /drivers/iommu/intel/iommu.c | |
parent | 4419da5d5d4b1788568b7bf22c083ba2832891df (diff) | |
parent | 42226c989789d8da4af1de0c31070c96726d990c (diff) | |
download | linux-stable-d6da35e0c6d50f76eaf11a0496d3d2ec1a1fea3f.tar.gz linux-stable-d6da35e0c6d50f76eaf11a0496d3d2ec1a1fea3f.tar.bz2 linux-stable-d6da35e0c6d50f76eaf11a0496d3d2ec1a1fea3f.zip |
Merge 5.18-rc7 into usb-next
We need the tty fixes in here as well, as we need to revert one of them :(
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/iommu/intel/iommu.c')
-rw-r--r-- | drivers/iommu/intel/iommu.c | 27 |
1 files changed, 24 insertions, 3 deletions
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index df5c62ecf942..0ea47e17b379 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -1588,7 +1588,8 @@ static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, unsigned long pfn, unsigned int pages, int ih, int map) { - unsigned int mask = ilog2(__roundup_pow_of_two(pages)); + unsigned int aligned_pages = __roundup_pow_of_two(pages); + unsigned int mask = ilog2(aligned_pages); uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT; u16 did = domain->iommu_did[iommu->seq_id]; @@ -1600,10 +1601,30 @@ static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, if (domain_use_first_level(domain)) { qi_flush_piotlb(iommu, did, PASID_RID2PASID, addr, pages, ih); } else { + unsigned long bitmask = aligned_pages - 1; + + /* + * PSI masks the low order bits of the base address. If the + * address isn't aligned to the mask, then compute a mask value + * needed to ensure the target range is flushed. + */ + if (unlikely(bitmask & pfn)) { + unsigned long end_pfn = pfn + pages - 1, shared_bits; + + /* + * Since end_pfn <= pfn + bitmask, the only way bits + * higher than bitmask can differ in pfn and end_pfn is + * by carrying. This means after masking out bitmask, + * high bits starting with the first set bit in + * shared_bits are all equal in both pfn and end_pfn. + */ + shared_bits = ~(pfn ^ end_pfn) & ~bitmask; + mask = shared_bits ? __ffs(shared_bits) : BITS_PER_LONG; + } + /* * Fallback to domain selective flush if no PSI support or - * the size is too big. PSI requires page size to be 2 ^ x, - * and the base address is naturally aligned to the size. + * the size is too big. */ if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap)) |