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| author | James Hogan <james.hogan@imgtec.com> | 2015-01-29 11:14:08 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-03-31 12:04:12 +0200 |
| commit | b720fd8b66151a8bdf6ec1be32c338d73592ff15 (patch) | |
| tree | eaa54d5c015f9599155b5010c9b7eca051c39721 /drivers/irqchip | |
| parent | 8f7ff027965619b17488141a5f39d14c850696ab (diff) | |
| download | linux-stable-b720fd8b66151a8bdf6ec1be32c338d73592ff15.tar.gz linux-stable-b720fd8b66151a8bdf6ec1be32c338d73592ff15.tar.bz2 linux-stable-b720fd8b66151a8bdf6ec1be32c338d73592ff15.zip | |
irqchip: mips-gic: Don't treat FDC IRQ as percpu devid
Treat the Fast Debug Channel (FDC) interrupt the same as the timer and
performance counter interrupts. Like them, the FDC IRQ is also per-VPE,
and also doesn't use a per-CPU device ID yet. Per-CPU device IDs don't
seem to work with IRQF_SHARED which is needed for compatibility with
cores which don't route the FDC IRQ through the GIC. For hardware which
routes FDC IRQs through the GIC this is something that could be added
later.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9141/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'drivers/irqchip')
| -rw-r--r-- | drivers/irqchip/irq-mips-gic.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index ef09a914a3b6..c8699eec3930 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -592,15 +592,20 @@ static int gic_local_irq_domain_map(struct irq_domain *d, unsigned int virq, * of the MIPS kernel code does not use the percpu IRQ API for * the CP0 timer and performance counter interrupts. */ - if (intr != GIC_LOCAL_INT_TIMER && intr != GIC_LOCAL_INT_PERFCTR) { + switch (intr) { + case GIC_LOCAL_INT_TIMER: + case GIC_LOCAL_INT_PERFCTR: + case GIC_LOCAL_INT_FDC: + irq_set_chip_and_handler(virq, + &gic_all_vpes_local_irq_controller, + handle_percpu_irq); + break; + default: irq_set_chip_and_handler(virq, &gic_local_irq_controller, handle_percpu_devid_irq); irq_set_percpu_devid(virq); - } else { - irq_set_chip_and_handler(virq, - &gic_all_vpes_local_irq_controller, - handle_percpu_irq); + break; } spin_lock_irqsave(&gic_lock, flags); |