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authorMoudy Ho <moudy.ho@mediatek.com>2023-03-27 11:13:30 +0800
committerHans Verkuil <hverkuil-cisco@xs4all.nl>2023-04-11 17:17:46 +0200
commit50709e6343e325c61dd7612afddfd8f38c8eba7c (patch)
tree85f4911755ba00080951f6bc0f7e79c5ace7f2f2 /drivers/media/pci/tw68
parentb35bf333ff8e7ad6bf4fb40257e27f989ad51cf3 (diff)
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media: platform: mtk-mdp3: chip config split about pipe info
In MDP3, a pipe is used to represent a data path which consisting of different components and MUTEX, as shown in the following diagram: +----------------------------+ | MUTEX [*1] | +----------------------------+ S ^ S ^ S ^ S ^ S ^ | | | | | | | | | | | | | | | | | | | | +--------------+ | | | | | | | | +-------------+ | +--------------+ | | | | | | +-------------+ | | | +------+ | | | | +------+ | | | | | +------+ | | +------+ | | | | | | | | | | | | | | | | | | | | | | | v E v E v E v E v E +-------+ +-----+ +-------+ +-----+ +-------+ B>--->| RDMA0 |>-->| PQ |>-->| RSZ0 |>-->| PQ |>-->| WROT0 |>-->B +-------+ +-----+ +-------+ +-----+ +-------+ [*1] MUTEX is SOF/EOF signal controller [*2] S = Start of frame (SOF) [*3] E = End of frame (EOF) [*4] B = frame buffer More pipes will be introduced in future chips for applications such as higher frame rate frequency, which should integrate and reorder related information into specific chip config file. Signed-off-by: Moudy Ho <moudy.ho@mediatek.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Diffstat (limited to 'drivers/media/pci/tw68')
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