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| author | Jan Kotas <jank@cadence.com> | 2019-07-22 04:22:22 -0400 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab+samsung@kernel.org> | 2019-07-25 06:43:01 -0400 |
| commit | 6ded416d4ac4ecbf104b897661cdfa2cdacf022a (patch) | |
| tree | 963e756610e111613fb267be99ba0f7e1fdc68bd /drivers/media/platform/cadence | |
| parent | bf9df90b3557ec6d5d92914da6a61453741d3e13 (diff) | |
| download | linux-stable-6ded416d4ac4ecbf104b897661cdfa2cdacf022a.tar.gz linux-stable-6ded416d4ac4ecbf104b897661cdfa2cdacf022a.tar.bz2 linux-stable-6ded416d4ac4ecbf104b897661cdfa2cdacf022a.zip | |
media: Fix Lane mapping in Cadence CSI2TX
This patch fixes mapping of lanes in DPHY_CFG register
of the controller. In the register, bit 0 means first data lane.
In Linux we currently assume lane 0 is clock.
Signed-off-by: Jan Kotas <jank@cadence.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Diffstat (limited to 'drivers/media/platform/cadence')
| -rw-r--r-- | drivers/media/platform/cadence/cdns-csi2tx.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/media/platform/cadence/cdns-csi2tx.c b/drivers/media/platform/cadence/cdns-csi2tx.c index 232259c71adf..c72c8a065428 100644 --- a/drivers/media/platform/cadence/cdns-csi2tx.c +++ b/drivers/media/platform/cadence/cdns-csi2tx.c @@ -236,7 +236,7 @@ static int csi2tx_start(struct csi2tx_priv *csi2tx) /* Put our lanes (clock and data) out of reset */ reg = CSI2TX_DPHY_CFG_CLK_RESET | CSI2TX_DPHY_CFG_MODE_LPDT; for (i = 0; i < csi2tx->num_lanes; i++) - reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i]); + reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i] - 1); writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG); udelay(10); @@ -244,7 +244,7 @@ static int csi2tx_start(struct csi2tx_priv *csi2tx) /* Enable our (clock and data) lanes */ reg |= CSI2TX_DPHY_CFG_CLK_ENABLE; for (i = 0; i < csi2tx->num_lanes; i++) - reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i]); + reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i] - 1); writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG); udelay(10); |