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| author | Marek Szyprowski <m.szyprowski@samsung.com> | 2017-03-23 09:03:25 +0100 |
|---|---|---|
| committer | Lee Jones <lee.jones@linaro.org> | 2017-04-27 09:25:07 +0100 |
| commit | 8f1be5bd14e8faf5a1255a32621601bb11a96232 (patch) | |
| tree | d1f09c00ebfa5b1792848121c0a90ecf4873eae3 /drivers/mfd | |
| parent | addebf1588ab812b891651ef5fba194659f71ea5 (diff) | |
| download | linux-stable-8f1be5bd14e8faf5a1255a32621601bb11a96232.tar.gz linux-stable-8f1be5bd14e8faf5a1255a32621601bb11a96232.tar.bz2 linux-stable-8f1be5bd14e8faf5a1255a32621601bb11a96232.zip | |
mfd: exynos-lpass: Add support for clocks
Exynos LPASS requires some clocks to be enabled to make any access to its
registers. This patch adds code for handling such clocks. For current set
of registers it is enough to keep sfr0_ctrl clock enabled. Till now it
worked only because those clocks were enabled by bootloader and driver
probe() happened before they were disabled by clock core because of lack
of users. Handling those clocks is also needed to make it possible to
enable support for audio power domain.
This patch requires adding sfr0_ctrl clock to device tree.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Diffstat (limited to 'drivers/mfd')
| -rw-r--r-- | drivers/mfd/exynos-lpass.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c index 39be39bbefc4..cbc4a48546c3 100644 --- a/drivers/mfd/exynos-lpass.c +++ b/drivers/mfd/exynos-lpass.c @@ -14,6 +14,7 @@ * only version 2 as published by the Free Software Foundation. */ +#include <linux/clk.h> #include <linux/delay.h> #include <linux/io.h> #include <linux/module.h> @@ -53,6 +54,7 @@ struct exynos_lpass { /* pointer to the LPASS TOP regmap */ struct regmap *top; + struct clk *sfr0_clk; }; static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask) @@ -72,6 +74,8 @@ static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask) static void exynos_lpass_enable(struct exynos_lpass *lpass) { + clk_prepare_enable(lpass->sfr0_clk); + /* Unmask SFR, DMA and I2S interrupt */ regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S); @@ -89,6 +93,8 @@ static void exynos_lpass_disable(struct exynos_lpass *lpass) /* Mask any unmasked IP interrupt sources */ regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0); regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0); + + clk_disable_unprepare(lpass->sfr0_clk); } static const struct regmap_config exynos_lpass_reg_conf = { @@ -115,6 +121,10 @@ static int exynos_lpass_probe(struct platform_device *pdev) if (IS_ERR(base_top)) return PTR_ERR(base_top); + lpass->sfr0_clk = devm_clk_get(dev, "sfr0_ctrl"); + if (IS_ERR(lpass->sfr0_clk)) + return PTR_ERR(lpass->sfr0_clk); + lpass->top = regmap_init_mmio(dev, base_top, &exynos_lpass_reg_conf); if (IS_ERR(lpass->top)) { |