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author | Omer Shpigelman <oshpigelman@habana.ai> | 2020-03-01 19:59:39 +0200 |
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committer | Oded Gabbay <oded.gabbay@gmail.com> | 2020-05-17 12:06:22 +0300 |
commit | 1fa185c6560cd15c1bf8840e7d157a29429279eb (patch) | |
tree | 4963f26ad91ddc78880bcafbf58bc28f33a04d19 /drivers/misc/habanalabs/habanalabs.h | |
parent | 76cedc739d7aac461ae303ca0e8b3a81e6ae00aa (diff) | |
download | linux-stable-1fa185c6560cd15c1bf8840e7d157a29429279eb.tar.gz linux-stable-1fa185c6560cd15c1bf8840e7d157a29429279eb.tar.bz2 linux-stable-1fa185c6560cd15c1bf8840e7d157a29429279eb.zip |
habanalabs: re-factor H/W queues initialization
We want to remove the following restrictions/assumptions in our driver:
1. The H/W queue index is also the completion queue index.
2. The H/W queue index is also the IRQ number of the completion queue.
3. All queues of the same type have consecutive indexes.
Therefore we add the support for H/W queues of the same type with
nonconsecutive indexes and completion queue index and IRQ number different
than the H/W queue index.
Signed-off-by: Omer Shpigelman <oshpigelman@habana.ai>
Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Diffstat (limited to 'drivers/misc/habanalabs/habanalabs.h')
-rw-r--r-- | drivers/misc/habanalabs/habanalabs.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/misc/habanalabs/habanalabs.h b/drivers/misc/habanalabs/habanalabs.h index ae3db8eb2fb5..299add419e79 100644 --- a/drivers/misc/habanalabs/habanalabs.h +++ b/drivers/misc/habanalabs/habanalabs.h @@ -365,6 +365,8 @@ struct hl_cs_job; * @pi: holds the queue's pi value. * @ci: holds the queue's ci value, AS CALCULATED BY THE DRIVER (not real ci). * @hw_queue_id: the id of the H/W queue. + * @cq_id: the id for the corresponding CQ for this H/W queue. + * @msi_vec: the IRQ number of the H/W queue. * @int_queue_len: length of internal queue (number of entries). * @valid: is the queue valid (we have array of 32 queues, not all of them * exists). @@ -377,6 +379,8 @@ struct hl_hw_queue { u32 pi; u32 ci; u32 hw_queue_id; + u32 cq_id; + u32 msi_vec; u16 int_queue_len; u8 valid; }; @@ -534,6 +538,7 @@ enum hl_pll_frequency { * @wreg: Write a register. Needed for simulator support. * @halt_coresight: stop the ETF and ETR traces. * @get_clk_rate: Retrieve the ASIC current and maximum clock rate in MHz + * @get_queue_id_for_cq: Get the H/W queue id related to the given CQ index. */ struct hl_asic_funcs { int (*early_init)(struct hl_device *hdev); @@ -620,6 +625,7 @@ struct hl_asic_funcs { void (*wreg)(struct hl_device *hdev, u32 reg, u32 val); void (*halt_coresight)(struct hl_device *hdev); int (*get_clk_rate)(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk); + u32 (*get_queue_id_for_cq)(struct hl_device *hdev, u32 cq_idx); }; |