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authorAndy Tang <andy.tang@nxp.com>2022-12-02 15:59:05 +0800
committerUlf Hansson <ulf.hansson@linaro.org>2022-12-07 13:29:14 +0100
commitc8d2d76d7646dc9b2d377699f68dce5403ad9b80 (patch)
tree21e9ec0c5bc507bb543ba0a1f155df50f6946be8 /drivers/mmc
parent496182a389627a60d1b12be32d1640b14c678b8b (diff)
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mmc: sdhci-of-esdhc: limit the SDHC clock frequency
The highest clock frequency for eMMC HS200 mode on ls1043a is 116.7Mhz according to its specification. So add the limit to gate the frequency. Signed-off-by: Andy Tang <andy.tang@nxp.com> Link: https://lore.kernel.org/r/20221202075905.25363-1-andy.tang@nxp.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/sdhci-of-esdhc.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
index e0266638381d..9d875bb531a8 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -42,6 +42,12 @@ static const struct esdhc_clk_fixup ls1021a_esdhc_clk = {
.max_clk[MMC_TIMING_SD_HS] = 46500000,
};
+static const struct esdhc_clk_fixup ls1043a_esdhc_clk = {
+ .sd_dflt_max_clk = 25000000,
+ .max_clk[MMC_TIMING_UHS_SDR104] = 116700000,
+ .max_clk[MMC_TIMING_MMC_HS200] = 116700000,
+};
+
static const struct esdhc_clk_fixup ls1046a_esdhc_clk = {
.sd_dflt_max_clk = 25000000,
.max_clk[MMC_TIMING_UHS_SDR104] = 167000000,
@@ -63,6 +69,7 @@ static const struct esdhc_clk_fixup p1010_esdhc_clk = {
static const struct of_device_id sdhci_esdhc_of_match[] = {
{ .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk},
+ { .compatible = "fsl,ls1043a-esdhc", .data = &ls1043a_esdhc_clk},
{ .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk},
{ .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk},
{ .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk},