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author | Tariq Toukan <tariqt@mellanox.com> | 2020-06-16 15:15:06 +0300 |
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committer | Saeed Mahameed <saeedm@mellanox.com> | 2020-06-27 14:00:23 -0700 |
commit | 0419d8c9d8f8d825576a41b2bb1e6043f34d1ae0 (patch) | |
tree | d26baee1a4837e94a4619a764012eace1dd6404c /drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h | |
parent | ed9b7646b06a2ed2450dd9437fc7d1ad2783140c (diff) | |
download | linux-stable-0419d8c9d8f8d825576a41b2bb1e6043f34d1ae0.tar.gz linux-stable-0419d8c9d8f8d825576a41b2bb1e6043f34d1ae0.tar.bz2 linux-stable-0419d8c9d8f8d825576a41b2bb1e6043f34d1ae0.zip |
net/mlx5e: kTLS, Add kTLS RX resync support
Implement the RX resync procedure, using the TLS async resync API.
The HW offload of TLS decryption in RX side might get out-of-sync
due to out-of-order reception of packets.
This requires SW intervention to update the HW context and get it
back in-sync.
Performance:
CPU: Intel(R) Xeon(R) CPU E5-2687W v4 @ 3.00GHz, 24 cores, HT off
NIC: ConnectX-6 Dx 100GbE dual port
Goodput (app-layer throughput) comparison:
+---------------+-------+-------+---------+
| # connections | 1 | 4 | 8 |
+---------------+-------+-------+---------+
| SW (Gbps) | 7.26 | 24.70 | 50.30 |
+---------------+-------+-------+---------+
| HW (Gbps) | 18.50 | 64.30 | 92.90 |
+---------------+-------+-------+---------+
| Speedup | 2.55x | 2.56x | 1.85x * |
+---------------+-------+-------+---------+
* After linerate is reached, diff is observed in CPU util.
Signed-off-by: Tariq Toukan <tariqt@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h')
-rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h b/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h index 7f55bd3229f1..e9d4a61b6bbb 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h @@ -14,6 +14,7 @@ enum mlx5e_icosq_wqe_type { #ifdef CONFIG_MLX5_EN_TLS MLX5E_ICOSQ_WQE_UMR_TLS, MLX5E_ICOSQ_WQE_SET_PSV_TLS, + MLX5E_ICOSQ_WQE_GET_PSV_TLS, #endif }; @@ -122,6 +123,9 @@ struct mlx5e_icosq_wqe_info { struct { struct mlx5e_ktls_offload_context_rx *priv_rx; } tls_set_params; + struct { + struct mlx5e_ktls_rx_resync_buf *buf; + } tls_get_params; #endif }; }; |