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author | Khalid Manaa <khalidm@nvidia.com> | 2022-01-26 14:14:58 +0200 |
---|---|---|
committer | Saeed Mahameed <saeedm@nvidia.com> | 2022-02-01 20:59:41 -0800 |
commit | b8d91145ed7cfa046cc07bcfb277465b9d45da73 (patch) | |
tree | 538a42f0ba3469bafb4acabd7639cda07e6cb9d0 /drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h | |
parent | 880b517691908fb753019b9b27cd082e7617debd (diff) | |
download | linux-stable-b8d91145ed7cfa046cc07bcfb277465b9d45da73.tar.gz linux-stable-b8d91145ed7cfa046cc07bcfb277465b9d45da73.tar.bz2 linux-stable-b8d91145ed7cfa046cc07bcfb277465b9d45da73.zip |
net/mlx5e: Fix wrong calculation of header index in HW_GRO
The HW doesn't wrap the CQE.shampo.header_index field according to the
headers buffer size, instead it always increases it until reaching overflow
of u16 size.
Thus the mlx5e_handle_rx_cqe_mpwrq_shampo handler should mask the
CQE header_index field to find the actual header index in the headers buffer.
Fixes: f97d5c2a453e ("net/mlx5e: Add handle SHAMPO cqe support")
Signed-off-by: Khalid Manaa <khalidm@nvidia.com>
Reviewed-by: Tariq Toukan <tariqt@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h')
-rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h b/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h index 4cdf8e5b24c2..b789af07829c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h @@ -167,6 +167,11 @@ static inline u16 mlx5e_txqsq_get_next_pi(struct mlx5e_txqsq *sq, u16 size) return pi; } +static inline u16 mlx5e_shampo_get_cqe_header_index(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) +{ + return be16_to_cpu(cqe->shampo.header_entry_index) & (rq->mpwqe.shampo->hd_per_wq - 1); +} + struct mlx5e_shampo_umr { u16 len; }; |