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| author | Tariq Toukan <tariqt@mellanox.com> | 2020-06-16 15:15:06 +0300 |
|---|---|---|
| committer | Saeed Mahameed <saeedm@mellanox.com> | 2020-06-27 14:00:23 -0700 |
| commit | 0419d8c9d8f8d825576a41b2bb1e6043f34d1ae0 (patch) | |
| tree | d26baee1a4837e94a4619a764012eace1dd6404c /drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_txrx.c | |
| parent | ed9b7646b06a2ed2450dd9437fc7d1ad2783140c (diff) | |
| download | linux-stable-0419d8c9d8f8d825576a41b2bb1e6043f34d1ae0.tar.gz linux-stable-0419d8c9d8f8d825576a41b2bb1e6043f34d1ae0.tar.bz2 linux-stable-0419d8c9d8f8d825576a41b2bb1e6043f34d1ae0.zip | |
net/mlx5e: kTLS, Add kTLS RX resync support
Implement the RX resync procedure, using the TLS async resync API.
The HW offload of TLS decryption in RX side might get out-of-sync
due to out-of-order reception of packets.
This requires SW intervention to update the HW context and get it
back in-sync.
Performance:
CPU: Intel(R) Xeon(R) CPU E5-2687W v4 @ 3.00GHz, 24 cores, HT off
NIC: ConnectX-6 Dx 100GbE dual port
Goodput (app-layer throughput) comparison:
+---------------+-------+-------+---------+
| # connections | 1 | 4 | 8 |
+---------------+-------+-------+---------+
| SW (Gbps) | 7.26 | 24.70 | 50.30 |
+---------------+-------+-------+---------+
| HW (Gbps) | 18.50 | 64.30 | 92.90 |
+---------------+-------+-------+---------+
| Speedup | 2.55x | 2.56x | 1.85x * |
+---------------+-------+-------+---------+
* After linerate is reached, diff is observed in CPU util.
Signed-off-by: Tariq Toukan <tariqt@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_txrx.c')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_txrx.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_txrx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_txrx.c index c1f1ad32ca4c..ac29aeb8af49 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_txrx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ktls_txrx.c @@ -22,7 +22,7 @@ enum { static void fill_static_params(struct mlx5_wqe_tls_static_params_seg *params, struct tls12_crypto_info_aes_gcm_128 *info, - u32 key_id) + u32 key_id, u32 resync_tcp_sn) { char *initial_rn, *gcm_iv; u16 salt_sz, rec_seq_sz; @@ -47,6 +47,7 @@ fill_static_params(struct mlx5_wqe_tls_static_params_seg *params, MLX5_SET(tls_static_params, ctx, const_2, 2); MLX5_SET(tls_static_params, ctx, encryption_standard, MLX5E_ENCRYPTION_STANDARD_TLS); + MLX5_SET(tls_static_params, ctx, resync_tcp_sn, resync_tcp_sn); MLX5_SET(tls_static_params, ctx, dek_index, key_id); } @@ -54,7 +55,7 @@ void mlx5e_ktls_build_static_params(struct mlx5e_set_tls_static_params_wqe *wqe, u16 pc, u32 sqn, struct tls12_crypto_info_aes_gcm_128 *info, - u32 tis_tir_num, u32 key_id, + u32 tis_tir_num, u32 key_id, u32 resync_tcp_sn, bool fence, enum tls_offload_ctx_dir direction) { struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl; @@ -74,7 +75,7 @@ mlx5e_ktls_build_static_params(struct mlx5e_set_tls_static_params_wqe *wqe, ucseg->flags = MLX5_UMR_INLINE; ucseg->bsf_octowords = cpu_to_be16(MLX5_ST_SZ_BYTES(tls_static_params) / 16); - fill_static_params(&wqe->params, info, key_id); + fill_static_params(&wqe->params, info, key_id, resync_tcp_sn); } static void |