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author | Moshe Shemesh <moshe@nvidia.com> | 2022-10-26 14:51:40 +0100 |
---|---|---|
committer | Jakub Kicinski <kuba@kernel.org> | 2022-10-27 11:06:35 -0700 |
commit | 212b4d7251c169f87fa734e79bdec8dd413be5cf (patch) | |
tree | 7d901526a170663ea881acfa8a3f548abce13f56 /drivers/net/ethernet/mellanox/mlx5 | |
parent | 888be6b279b7257b5f6e4c9527675bff0a335596 (diff) | |
download | linux-stable-212b4d7251c169f87fa734e79bdec8dd413be5cf.tar.gz linux-stable-212b4d7251c169f87fa734e79bdec8dd413be5cf.tar.bz2 linux-stable-212b4d7251c169f87fa734e79bdec8dd413be5cf.zip |
net/mlx5: Wait for firmware to enable CRS before pci_restore_state
After firmware reset driver should verify firmware already enabled CRS
and became responsive to pci config cycles before restoring pci state.
Fix that by waiting till device_id is readable through PCI again.
Fixes: eabe8e5e88f5 ("net/mlx5: Handle sync reset now event")
Signed-off-by: Moshe Shemesh <moshe@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Link: https://lore.kernel.org/r/20221026135153.154807-3-saeed@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlx5')
-rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c b/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c index e8896f368362..07c583996c29 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c @@ -358,6 +358,23 @@ static int mlx5_pci_link_toggle(struct mlx5_core_dev *dev) err = -ETIMEDOUT; } + do { + err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, ®16); + if (err) + return err; + if (reg16 == dev_id) + break; + msleep(20); + } while (!time_after(jiffies, timeout)); + + if (reg16 == dev_id) { + mlx5_core_info(dev, "Firmware responds to PCI config cycles again\n"); + } else { + mlx5_core_err(dev, "Firmware is not responsive (0x%04x) after %llu ms\n", + reg16, mlx5_tout_ms(dev, PCI_TOGGLE)); + err = -ETIMEDOUT; + } + restore: list_for_each_entry(sdev, &bridge_bus->devices, bus_list) { pci_cfg_access_unlock(sdev); |