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| author | Amit Cohen <amcohen@nvidia.com> | 2024-04-02 15:54:21 +0200 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2024-04-03 19:50:40 -0700 |
| commit | 7bc6a3098c3821b50e9ef54e22a1a9d701f6fe00 (patch) | |
| tree | b7a1b68dc56b11abfcb2c60aa70b0597f29e64a4 /drivers/net/ethernet/mellanox/mlxsw/pci_hw.h | |
| parent | d4b3930b19f7339c3fb98fc3ed71388b0180e7a7 (diff) | |
| download | linux-stable-7bc6a3098c3821b50e9ef54e22a1a9d701f6fe00.tar.gz linux-stable-7bc6a3098c3821b50e9ef54e22a1a9d701f6fe00.tar.bz2 linux-stable-7bc6a3098c3821b50e9ef54e22a1a9d701f6fe00.zip | |
mlxsw: pci: Rename MLXSW_PCI_EQS_COUNT
Currently we use MLXSW_PCI_EQS_COUNT event queues. A next patch will
change the driver to initialize only EQ1, as EQ0 is not required anymore
when we poll command interface.
Rename the macro to MLXSW_PCI_EQS_MAX as later we will not initialize
the maximum supported EQs, this value represents the maximum and a new
macro will be added to represent the actual used queues.
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: Petr Machata <petrm@nvidia.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://lore.kernel.org/r/b08df430b62f23ca1aa3aaa257896d2d95aa7691.1712062203.git.petrm@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlxsw/pci_hw.h')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlxsw/pci_hw.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h b/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h index 7cdf0ce24f28..32a4f436d24d 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h +++ b/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h @@ -42,7 +42,7 @@ ((offset) + (type_offset) + (num) * 4) #define MLXSW_PCI_CQS_MAX 96 -#define MLXSW_PCI_EQS_COUNT 2 +#define MLXSW_PCI_EQS_MAX 2 #define MLXSW_PCI_EQ_ASYNC_NUM 0 #define MLXSW_PCI_EQ_COMP_NUM 1 |