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| author | Amit Cohen <amcohen@nvidia.com> | 2022-07-24 11:03:25 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2022-07-25 13:58:55 +0100 |
| commit | 9468322963894fd7a6138f9bfe3aca88129738d8 (patch) | |
| tree | 3df514deba5e1d9d1126aad49c400999cb6fe64f /drivers/net/ethernet/mellanox/mlxsw/pci_hw.h | |
| parent | 22d950b79ea70b69386b3b131051fbe22f065bdf (diff) | |
| download | linux-stable-9468322963894fd7a6138f9bfe3aca88129738d8.tar.gz linux-stable-9468322963894fd7a6138f9bfe3aca88129738d8.tar.bz2 linux-stable-9468322963894fd7a6138f9bfe3aca88129738d8.zip | |
mlxsw: pci: Simplify FRC clock reading
Currently, the reading of FRC values (high and low) is done using macro
which calls to a function. In addition, to calculate the offset of FRC,
a simple macro is used. This code can be simplified by adding an helper
function and calculating the offset explicitly instead of using an
additional macro for that.
Add the helper function and convert the existing code. This helper will be
used later to read UTC clock.
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlxsw/pci_hw.h')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlxsw/pci_hw.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h b/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h index 543eb8c8a983..48dbfea0a2a1 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h +++ b/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h @@ -41,9 +41,6 @@ #define MLXSW_PCI_DOORBELL(offset, type_offset, num) \ ((offset) + (type_offset) + (num) * 4) -#define MLXSW_PCI_FREE_RUNNING_CLOCK_H(offset) (offset) -#define MLXSW_PCI_FREE_RUNNING_CLOCK_L(offset) ((offset) + 4) - #define MLXSW_PCI_CQS_MAX 96 #define MLXSW_PCI_EQS_COUNT 2 #define MLXSW_PCI_EQ_ASYNC_NUM 0 |